Formation of Through Via before Contact Processing

• US 20110177655A1
• Filed: 03/29/2011
• Published: 07/21/2011
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Granted Patent: US 9,209,157 B2
• Time in Patent Office: Days
• US Class Current: 438/119
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to contact or metallization processing. Contacts and bonding pads may then be fabricated after the TSVs are already in place, which allows the TSV to be more dense and allows more freedom in the overall TSV design. By providing a denser connection between TSVs and bonding pads, individual wafers and dies may be bonded directly at the bonding pads. The conductive bonding material, thus, maintains an electrical connection to the TSVs and other IC components through the bonding pads.

Claims

1. A method for forming one or more through vias comprising:

forming active devices on a front-side of a first wafer, the first wafer comprising a back-side opposite the front-side of the first wafer;

forming one or more recesses in the first wafer prior to forming an interlayer dielectric (ILD) layer over the front-side of the first wafer, the one or more recesses extending from the front-side of the first wafer to a predetermined distance from the back-side of the first wafer;

forming conductive material in the one or more recesses, the conducting material forming one or more through vias; and

forming a metallization layer over the back-side of the first wafer, the metallization layer comprising a first contact electrically connected to at least one of the one or more through vias and also being exposed to allow current to flow to at least one of the one or more through vias.

2. The method of claim 1, further comprising:

forming the ILD layer on the front-side over the one or more through vias; and

forming a second contact in the ILD layer, wherein the second contact has an electrical connection to one or more of the one or more through vias.

3. The method of claim 2, further comprising aligning the second contact with the one or more through vias.

4. The method of claim 2, wherein the forming the second contact comprises forming multiple contacts in connection with one of the one or more through vias.

5. The method of claim 2, further comprising:

forming one or more intermetal dielectric (IMD) layers over the ILD layer and the second contact; and

forming a first bonding pad in an uppermost IMD layer of the one or more IMD layers, wherein the first bonding pad has an electrical connection to the second contact.

6. The method of claim 5, further comprising exposing one or more back-side contacts of the one or more through vias by removing an amount of substrate material from the back-side of the first wafer, wherein the amount is either equivalent to the predetermined distance or greater than the predetermined distance, such that the one or more through vias protrude from the back-side of the first wafer.

7. The method of claim 5, further comprising bonding a second wafer to the first wafer, the bonding comprising:

aligning the first bonding pad with a second bonding pad on the second wafer; and

generating an adhesion between the first bonding pad and the second bonding pad.

8. The method of claim 7, wherein the generating the adhesion comprises applying a bonding medium between the first bonding pad and the second bonding pad.

9. The method of claim 8, wherein the bonding medium consists essentially of a material selected from the group consisting of copper, tungsten, copper-tin alloy, gold-tin alloy, indium-gold alloy, and lead-tin alloy.

10. The method of claim 8, further comprising bonding a third wafer to the back-side of the first wafer, wherein the third wafer is electrically connected to the first contact.

11. The method of claim 8, further comprising:

depositing a back-side ILD layer on the back-side of the first wafer;

removing portions of the back-side ILD to expose the first contact;

depositing a back-side IMD layer over the back-side ILD layer and the first contact; and

forming a third bonding pad in the back-side IMD layer, wherein the third bonding pad has an electrical connection to the first contact.

12. A method for bonding one or more wafers comprising:

positioning a first wafer, the first wafer having active devices and a first bonding pad connected to a first through silicon via (TSV), the first TSV extending through an internal portion of the first wafer;

positioning a second wafer in relation to the first wafer, the second wafer having a second bonding pad connected to a second TSV, the second TSV extending through the second wafer;

bonding the first bonding pad and the second bonding pad using a material that is electrically compatible with the first bonding pad and the second bonding pad; and

forming a third bonding pad on a back-side of the first wafer, the third bonding pad connected to the first TSV.

13. The method of claim 12, further comprising:

positioning a third wafer in relation to one of the first wafer and the second wafer, the third wafer having a third bonding pad connected to a third TSV, the third TSV providing electrical connection to one or more additional active devices on the third wafer; and

bonding the third bonding pad to one of either the first bonding pad or the second bonding pad using the material.

14. The method of claim 12, wherein the first TSV is formed prior to at least one of a contact process or a metallization process.

15. The method of claim 12, wherein the forming the third bonding pad further comprises:

removing a portion of substrate material on a back-side of the first wafer to expose a back-side connection to the first TSV; and

creating the third bonding pad electrically connected to the back-side connection.

16. The method of claim 15, further comprising bonding a fourth bonding pad of an third wafer to the third bonding pad using the material.

17. A method for forming a semiconductor device comprising:

forming a first through silicon via (TSV) in a first integrated circuit (IC) die, the first IC die comprising active devices located on a front-side;

after the forming the first TSV, processing the first IC die to add;

a first contact connected to the first TSV; and

a first bonding pad connected to the first contact;

forming a second TSV in a second IC die;

after the forming the second TSV, processing the second IC die to add;

a second contact connected to the second TSV; and

a second bonding pad connected to the second contact; and

bonding the first bonding pad to the second bonding pad using a rigid conducting material.

18. The method of claim 17, further comprising aligning the first contact with the first TSV.

19. The method of claim 17, further comprising removing a portion of substrate material on a back-side of the first IC die to expose a back-side connection to the first TSV.

20. The method of claim 19, further comprising:

creating one or more back-side bonding pads electrically connected to the back-side connection; and

bonding a third bonding pad of an additional IC die to the one or more back-side bonding pads using the rigid conducting material.