INDEPENDENT LINK AND BANK SELECTION

• US 20110179245A1
• Filed: 03/31/2011
• Published: 07/21/2011
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: PYEON, HONG BEOM, KIM, JIN-KI, OH, HAKJUNE
• Granted Patent: US 8,285,960 B2
• Time in Patent Office: Days
• US Class Current: 711/168
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Claims

1. A memory system comprising:

a plurality of memory banks, each memory bank having a respective at least one memory bank input and a respective at least one memory bank output;

a plurality of inputs;

a plurality of outputs;

first switching logic for selectably passing signals received on the plurality of inputs to memory bank inputs of the plurality of memory banks;

second switching logic for selectably passing signals received from memory bank outputs to the plurality of outputs; and

switch controller logic configured to control the selectably passing signals received on the plurality of inputs to memory bank inputs and the selectably passing signals received from memory bank outputs to the plurality of outputs to prevent simultaneous or overlapping passing of signals received at multiple inputs to the same memory bank, and to prevent simultaneous or overlapping passing of signals received from multiple memory bank outputs to the same output.

2. A method comprising:

receiving a plurality of inputs;

outputting a plurality of outputs;

selectably passing signals received on the plurality of inputs to memory bank inputs of a plurality of memory banks;

selectably passing signals received from memory bank outputs to the plurality of outputs; and

controlling the selectably passing signals received on the plurality of inputs to memory bank inputs and the selectably passing signals received from memory bank outputs to the plurality of outputs to prevent simultaneous or overlapping passing of signals received at multiple inputs to the same memory bank, and to prevent simultaneous or overlapping passing of signals received from multiple memory bank outputs to the same output.