Chip capacitor embedment method

• US 20110179642A1
• Filed: 03/30/2011
• Published: 07/28/2011
• Est. Priority Date: 09/28/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Park, Dae-Hyun, Han, Mi-Ja, Yoo, Je-Gwang, Kim, Han
• Application Number:
  US13/064,542
• Publication Number:
  US 20110179642A1
• Time in Patent Office: Days
• US Class Current: 29/841
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H05K 1/0231 Capacitors or dielectric substances
• CPC Class Codes: H05K 1/0236 Electromagnetic band-gap structures
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/093 Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein reduction of cross-talk, noise or interference by patterned shielding planes, ground planes or power planes H05K1/0224
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts branched layout H05K2201/09254
• CPC Class Codes: H05K 2201/10636 Leadless chip, e.g. chip capacitor or resistor
• CPC Class Codes: H05K 2201/10643 Disc shaped leadless component
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.

Abstract

A method of embedding a chip capacitor in a printed circuit board including a first conductive layer and a dielectric layer placed on the first conductive layer includes removing the dielectric layer to form a cavity exposing the first conductive layer; seating a chip capacitor in the cavity; filling a filled material at a space excluding a space occupied by the chip capacitor in the cavity; forming a via penetrating the filled material and being connected to the chip capacitor; and stacking a conductive material to constitute a second conductive layer in surfaces of the via and the dielectric layer and in an surface of the filled material filled in the cavity.

Claims

1. A method of embedding a chip capacitor in a printed circuit board including a first conductive layer and a dielectric layer placed on the first conductive layer, the method comprising:

removing the dielectric layer to form a cavity exposing the first conductive layer;

seating a chip capacitor in the cavity;

filling a filled material at a space excluding a space occupied by the chip capacitor in the cavity;

forming a via penetrating the filled material and being connected to the chip capacitor; and

stacking a conductive material to constitute a second conductive layer in surfaces of the via and the dielectric layer and in an surface of the filled material filled in the cavity.

2. The method of claim 1, wherein the chip capacitor comprises a first electrode, a dielectric member, placed on the first electrode, and a second electrode, placed on the dielectric member, and

the first electrode is connected to the first conductive layer, and the second electrode is connected to the second conductive layer through the via.

3. The method of claim 1, further comprising:

forming an etched pattern in an open-curved line shape in a surrounding area of a part corresponding to a position in which the cavity is supposed to be formed in the first conductive layer.

4. The method of claim 1, wherein the etched pattern has a spiral shape.

5. The method of claim 1, further comprising:

forming an etched pattern in an open-curved line shape in a surrounding area of a part corresponding to a position in which the via is formed in the second conductive layer.

6. The method of claim 1, wherein the etched pattern has a spiral shape.