DISPLAY DEVICE

• US 20110180794A1
• Filed: 01/21/2011
• Published: 07/28/2011
• Est. Priority Date: 01/24/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 8,879,010 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/133753 with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/10 semiconductor
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 50/12 comprising dopants
• CPC Class Codes: H10K 50/19 Tandem OLEDs
• CPC Class Codes: H10K 59/32 Stacked devices having two or more layers, each emitting at different wavelengths

Abstract

A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a plurality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10 zA/μm at room temperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100 zA/μm per micrometer in the channel width.

Claims

1. A display device comprising:

a plurality of pixels provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits,

wherein the plurality of subunits each comprise;

a transistor which comprises a semiconductor layer including an oxide semiconductor adjacent to a gate electrode with an insulating layer interposed therebetween;

a source electrode and a drain electrode, which are electrically connected to the semiconductor layer; and

a liquid crystal element electrically connected to the transistor.

2. The display device according to claim 1, further comprising a lighting unit adjacent to the plurality of pixels,

wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.

3. The display device according to claim 1, further comprising:

a first alignment film and a second alignment film,

wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.

4. The display device according to claim 1,

wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.

5. The display device according to claim 1,

wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.

6. The display device according to claim 1,

wherein the source electrode and the drain electrode each comprise metal nitride.

7. The display device according to claim 1,

wherein the source electrode and the drain electrode each comprise tungsten nitride, titanium nitride, or molybdenum nitride.

8. The display device according to claim 1,

wherein a field-effect mobility of the transistor in an on state is higher than or equal to 10 cm²/Vsec and lower than or equal to 150 cm²/Vsec.

9. The display device according to claim 1,

wherein an off current of the transistor is lower than 10 zA/μ

m at room temperature and lower than 100 zA/μ

m at 85°

C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.

10. The display device according to claim 1,

wherein a channel formation region of the semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.

11. The display device according to claim 1, further comprising a storage capacitor, wherein a first terminal of the storage capacitor is electrically connected to a first terminal of the liquid crystal element, and a second terminal of the storage capacitor is electrically connected to a second terminal of the liquid crystal element.

12. A display device comprising:

a pixel portion in which a plurality of pixels are provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits; and

a driver circuit portion electrically connected to the pixel portion,

wherein the plurality of subunits each comprise;

a transistor which comprises a semiconductor layer including an oxide semiconductor adjacent to a gate electrode with an insulating layer interposed therebetween;

a source electrode and a drain electrode, which are electrically connected to the semiconductor layer; and

a liquid crystal element electrically connected to the transistor, and

wherein the driver circuit portion configured to apply an image signal to a selected pixel of the plurality of pixels.

13. The display device according to claim 12, further comprising a lighting unit adjacent to the plurality of pixels,

wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.

14. The display device according to claim 12, further comprising:

a first alignment film and a second alignment film,

wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.

15. The display device according to claim 12,

wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.

16. The display device according to claim 12,

wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.

17. The display device according to claim 12,

wherein the source electrode and the drain electrode each comprise metal nitride.

18. The display device according to claim 12,

wherein the source electrode and the drain electrode each comprise tungsten nitride, titanium nitride, or molybdenum nitride.

19. The display device according to claim 12,

wherein a field-effect mobility of the transistor in an on state is higher than or equal to 10 cm²/Vsec and lower than or equal to 150 cm²/Vsec.

20. The display device according to claim 12,

wherein an off current of the transistor is lower than 10 zA/μ

m at room temperature and lower than 100 zA/μ

m at 85°

C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.

21. The display device according to claim 12,

wherein a channel formation region of the semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.

22. The display device according to claim 12, further comprising a storage capacitor, wherein a first terminal of the storage capacitor is electrically connected to a first terminal of the liquid crystal element, and a second terminal of the storage capacitor is electrically connected to a second terminal of the liquid crystal element.

23. A display device comprising:

a pixel portion in which a plurality of pixels are provided in a matrix, the plurality of pixels each comprising one or more units, each unit comprising a plurality of subunits; and

a driver circuit portion electrically connected to the pixel portion,

wherein the plurality of subunits each comprise;

a transistor which comprises a semiconductor layer including an oxide semiconductor adjacent to a gate electrode with an insulating layer interposed therebetween;

a source electrode and a drain electrode, which are electrically connected to the semiconductor layer; and

a liquid crystal element electrically connected to the transistor, and

wherein the driver circuit portion configured to select a first operation mode in which an image signal is applied to a selected pixel of the plurality of pixels to display an image, or a second operation mode in which an application of an image signal is stopped and an image is held.

24. The display device according to claim 23, further comprising a lighting unit adjacent to the plurality of pixels,

wherein the lighting unit includes a light-emitting diode or an organic electroluminescence element.

25. The display device according to claim 23, further comprising:

a first alignment film and a second alignment film,

wherein the liquid crystal element is interposed between the first alignment film and the second alignment film.

26. The display device according to claim 23,

wherein an alignment mode of liquid crystal molecules of the liquid crystal element is any one of a twisted nematic (TN), a vertical alignment (VA) mode, a multi-domain vertical alignment (MVA) mode, an in-plane switching (IPS) mode, a continuous pinwheel alignment (CPA) mode, and a patterned vertical alignment (PVA) mode.

27. The display device according to claim 23,

wherein a liquid crystal phase of the liquid crystal element is any one of a nematic phase, a smectic phase, a cholesteric phase, and a blue phase.

28. The display device according to claim 23,

wherein the source electrode and the drain electrode each comprise metal nitride.

29. The display device according to claim 23,

wherein the source electrode and the drain electrode each comprise tungsten nitride, titanium nitride, or molybdenum nitride.

30. The display device according to claim 23,

wherein a field-effect mobility of the transistor in an on state is higher than or equal to 10 cm²/Vsec and lower than or equal to 150 cm²/Vsec.

31. The display device according to claim 23,

wherein an off current of the transistor is lower than 10 zA/μ

m at room temperature and lower than 100 zA/μ

m at 85°

C. in a range of a voltage for driving liquid crystal molecules of the liquid crystal element.

32. The display device according to claim 23,

wherein a channel formation region of the semiconductor layer includes an intrinsic oxide semiconductor or a substantially intrinsic oxide semiconductor.

33. The display device according to claim 23, further comprising a storage capacitor, wherein a first terminal of the storage capacitor is electrically connected to a first terminal of the liquid crystal element, and a second terminal of the storage capacitor is electrically connected to a second terminal of the liquid crystal element.