SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

• US 20110180847A1
• Filed: 09/23/2010
• Published: 07/28/2011
• Est. Priority Date: 01/22/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ikeda, Keiji, Moriyama, Yoshihiko, Tezuka, Tsutomu
• Granted Patent: US 8,242,568 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si_1-xGe_x (0<x<1) formed on the active area, and a fin structure of Si_1-yGe_y (x<y≦1) formed on the buffer layer. The fin structure has a side surface of a (110) plane perpendicular to the surface of the Si substrate and the width thereof in a direction perpendicular to the one direction of the fin structure is narrower than that of the buffer layer.

Claims

1. A semiconductor device comprising:

a convex active area formed along one direction on a surface region of a Si substrate,

a buffer layer formed on the convex active area, the buffer layer being made of Si_1-xGe_x (0<

x<

1), and

a fin structure formed on the buffer layer, the fin structure having a side surface perpendicular to the surface of the Si substrate, the fin structure being made of Si_1-yGe_y (x<

y≦

1), a width of the fin structure in a direction perpendicular to the one direction being narrower than that of the buffer layer and plane orientation of the side surface of the fin structure being (110).

2. The semiconductor device according to claim 1, further comprising a device isolation layer formed on the Si substrate to sandwich the convex active area, an uppermost surface of the device isolation layer being set above an uppermost surface of the buffer layer.

3. The semiconductor device according to claim 1, wherein the buffer layer is formed by relaxing lattice strain and the fin structure is formed to have lattice strain.

4. The semiconductor device according to claim 1, wherein Ge composition x of the buffer layer is set in a range of 0.7≦

x≦

0.9, and Ge composition y of the fin structure is set in a range of y≧

0.9 and y≧

x+1.

5. The semiconductor device according to claim 1, wherein the convex active area is formed in a plural form, the fin structures are formed on part of the convex active areas with the buffer layers disposed therebetween and the fin structures are directly formed on the remaining convex active areas.

6. The semiconductor device according to claim 1, wherein a plane orientation of the surface of the Si substrate is (100).

7. The semiconductor device according to claim 1, wherein a gate electrode is formed above the side surfaces and upper surface of the fin structure with a gate insulating film disposed therebetween and source/drain regions are formed in regions corresponding to the gate electrode in the fin structure.

8. The semiconductor device according to claim 7, wherein the fin structure, gate insulating film, gate electrode and source/drain regions configure a pMOSFET.

9. A fabrication method of a semiconductor device comprising:

forming convex active areas on a surface region of a Si substrate by forming a plurality of trenches that are long in one direction and are formed in parallel in the surface region of the Si substrate,

burying a first device isolation layer in the trenches,

etching the surface regions of the convex active areas with the first device isolation layer used as a mask,

growing a first semiconductor layer of Si_1-xGe_x (0<

x<

1) and a second semiconductor layer of Si_1-yGe_y (x<

y≦

1) in this order on the convex active areas with etched the surface regions,

removing the first device isolation layer after growing the first and second semiconductor layers,

narrowing a width of the second semiconductor layer in a direction perpendicular to the one direction and exposing a (110) plane perpendicular to the surface of the Si substrate to the side surface of the second semiconductor layer by etching the second semiconductor layer by an anisotropic wet etching method after removing the first device isolation layer, and

burying a second device isolation layer in the trenches after etching the second semiconductor layer.

10. The method according to claim 9, wherein the second device isolation layer is buried to a position higher than an uppermost surface of the second semiconductor layer.

11. The method according to claim 9, wherein the wet etching method for etching the second semiconductor layer comprises selectively etching the second semiconductor layer with respect to the Si substrate and the first semiconductor layer.

12. The method according to claim 9, wherein a mixed solution of ammonium hydroxide and hydrogen peroxide is used and a mol concentration ratio of ammonium hydroxide to hydrogen peroxide is set in a range of 6 to 552 when the second semiconductor layer is wet-etched.

13. The method according to claim 9, wherein a mixed solution of hydrogen chloride and hydrogen peroxide is used and a mol concentration ratio of hydrogen chloride to hydrogen peroxide is set in a range of 0.5 to 24 when the second semiconductor layer is wet-etched.

14. The method according to claim 9, wherein an etching process is performed by use of a first mixed solution that contains hydrogen chloride and hydrogen peroxide and in which a mol concentration ratio of hydrogen chloride to hydrogen peroxide is set in a range of 0.5 to 24 and then an etching process is performed by use of a second mixed solution that contains ammonium hydroxide and hydrogen peroxide and in which a mol concentration ratio of ammonium hydroxide to hydrogen peroxide is set in a range of 6 to 552 when the second semiconductor layer is wet-etched.

15. A fabrication method of a semiconductor device comprising:

forming a plurality of convex active areas on a surface region of a Si substrate by forming a plurality of trenches that are long in one direction and are formed in parallel in the surface region of the Si substrate,

burying a first device isolation layer in the trenches,

etching the surface region of the convex active areas with the first device isolation layer used as a mask,

forming oxide films on first active areas that are part of the convex active areas whose surface regions are etched,

growing a first semiconductor layer of Si_1-xGe_x (0<

x<

1) on second active areas that are the remaining part of the convex active areas with the oxide films used as a mask,

growing a second semiconductor layer of Si_1-yGe_y (x<

y≦

1) on the first semiconductor layer and the first active areas after the oxide films are removed,

removing the first device isolation layer after growing the second semiconductor layer,

narrowing a width of the second semiconductor layer in a direction perpendicular to the one direction and exposing a (110) plane perpendicular to the surface of the Si substrate to the side surface of the second semiconductor layer by etching the second semiconductor layer by use of an anisotropic wet etching method after removing the first device isolation layer,

burying a second device isolation layer in the trenches after etching the second semiconductor layer, and

forming nMOSFETs on the second semiconductor layer on the first active areas and forming pMOSFETs on the second semiconductor layer on the second active areas.

16. The method according to claim 15, wherein the second device isolation layer is buried to a position higher than an uppermost surface of the second semiconductor layer.

17. The method according to claim 15, wherein the wet etching method for etching the second semiconductor layer comprises selectively etching the second semiconductor layer with respect to the Si substrate and the first semiconductor layer.

18. The method according to claim 15, wherein a mixed solution of ammonium hydroxide and hydrogen peroxide is used and a mol concentration ratio of ammonium hydroxide to hydrogen peroxide is set in a range of 6 to 552 when the second semiconductor layer is wet-etched.

19. The method according to claim 15, wherein a mixed solution of hydrogen chloride and hydrogen peroxide is used and a mol concentration ratio of hydrogen chloride to hydrogen peroxide is set in a range of 0.5 to 24 when the second semiconductor layer is wet-etched.

20. The method according to claim 15, wherein an etching process is performed by use of a first mixed solution that contains hydrogen chloride and hydrogen peroxide and in which a mol concentration ratio of hydrogen chloride to hydrogen peroxide is set in a range of 0.5 to 24 and then an etching process is performed by use of a second mixed solution that contains ammonium hydroxide and hydrogen peroxide and in which a mol concentration ratio of ammonium hydroxide to hydrogen peroxide is set in a range of 6 to 552 when the second semiconductor layer is wet-etched.