SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20110180868A1
• Filed: 07/30/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: JANG, Kyoung Chul
• Granted Patent: US 8,278,201 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a recess on a semiconductor substrate;

forming a first gate electrode material and a sacrificial layer on an entire surface including;

etching the sacrificial layer and the first gate electrode material to form a first gate electrode pattern in a lower portion of the recess;

forming a second gate electrode material over the substrate and the first gate electrode defined within the recess; and

etching the second gate electrode material to form a second gate electrode pattern.

2. The method of claim 1, wherein the first gate electrode material includes any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof.

3. The method of claim 1, further comprising:

forming a sacrificial layer over the substrate prior to forming the first gate electrode material, the sacrificial layer including one selected from the group consisting of a polysilicon layer, an oxide layer, a photo resist film, a carbon layer and a combination thereof.

4. The method of claim 1, wherein the second gate electrode material is formed with a laminated structure of any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof, and

wherein the second gate electrode material includes tungsten W.

5. The method of claim 4, wherein the tungsten W layer has a larger width in an upper portion of the recess than in a lower portion of the recess.

6. The method of claim 1, wherein etching the second gate electrode material is performed by an etch back process.

7. A method of manufacturing a semiconductor device, comprising:

forming a recess on a semiconductor substrate, the recess having an upper portion and a lower portion;

forming a first gate electrode material over the recess;

etching the first gate electrode material to form the first gate electrode pattern on the lower portion of the recess, the first gate electrode pattern coating the lower portion of the recess;

forming a second gate electrode material within the upper and lower portions of the recess; and

etching the second gate electrode material to form a second gate electrode pattern extending at least partly into the lower portion of the recess, so that a portion of the second gate electrode is coated with the first gate electrode.

8. The method of claim 7, wherein the first gate electrode material is formed of any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof, and

wherein the second gate electrode material includes tungsten W.

9. The method of claim 7, wherein the second gate electrode pattern is formed by an etch back process.

10. A semiconductor device, comprising:

a recess formed on a semiconductor substrate;

a coating pattern coating a lower portion of the recess, the coating pattern being conductive material; and

a primarily gate electrode pattern formed within the recess including the lower portion thereof, wherein at least a lower portion of the gate electrode is coated by the coating pattern,

wherein the coating pattern and the primarily gate electrode pattern define a gate electrode.

11. The semiconductor device of claim 10, wherein the coating pattern includes any selected from the group consisting of TiN, TaN, Ti, Ta, Mo, Al and a combination thereof, and

wherein the primarily gate electrode material includes tungsten W.

12. The semiconductor device of claim 11, wherein the primarily gate electrode pattern has an upper portion that is wider than the lower portion thereof.