SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20110181321A1
• Filed: 01/19/2011
• Published: 07/28/2011
• Est. Priority Date: 01/26/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsudera, Katsuki
• Granted Patent: US 8,384,441 B2
• Time in Patent Office: Days
• US Class Current: 327/65
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A semiconductor integrated circuit has a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison. The semiconductor integrated circuit has a first switch circuit between a first reception terminal and the first noninverting input terminal. The semiconductor integrated circuit has a second switch circuit between a second reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a third switch circuit between the first reception terminal and the first inverting input terminal. The semiconductor integrated circuit has a fourth switch circuit between the second reception terminal and the first noninverting input terminal.

Claims

1. A semiconductor integrated circuit comprising:

a first reception terminal and a second reception terminal receiving a differential signal;

a squelch circuit which has a first noninverting input terminal and a first inverting input terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison;

a first switch circuit which brings about conduction between the first reception terminal and the first noninverting input terminal when it is switched to an on-state, and which brings about insulation between the first reception terminal and the first noninverting input terminal when it is switched to an off-state;

a second switch circuit which brings about conduction between the second reception terminal and the first inverting input terminal when it is switched to an on-state, and which brings about insulation between the second reception terminal and the first inverting input terminal when it is switched to an off-state;

a third switch circuit which brings about conduction between the first reception terminal and the first inverting input terminal when it is switched to an on-state, and which brings about insulation between the first reception terminal and the first inverting input terminal when it is switched to an off-state; and

a fourth switch circuit which brings about conduction between the second reception terminal and the first noninverting input terminal when it is switched to an on-state, and which brings about insulation between the second reception terminal and the first noninverting input terminal when it is switched to an off-state.

2. The semiconductor integrated circuit according to claim 1,

wherein at time of test operation of the squelch circuit,

in a state in which a first DC voltage is applied to the first reception terminal and a second DC voltage which is different from the first DC voltage is applied to the second reception terminal,

the first switch circuit and the second switch circuit are controlled to be synchronized to each other in on/off and the third switch circuit and the fourth switch circuit are controlled to be synchronized in on/off and be complementary in on/off to the first and second switch circuits.

5. The semiconductor integrated circuit according to claim 2, further comprising a pattern generator which is adapted to generate a test pattern signal,

wherein on/off of the first to fourth switch circuits are controlled on the basis of the test pattern signal.

7. The semiconductor integrated circuit according to claim 5, further comprising:

a serializer which conducts parallel-to-serial conversion on the test pattern signal supplied from the pattern generator and outputs a resultant signal; and

a driver which outputs the signal supplied from the serializer, as a differential signal,

wherein on/off of the first to fourth switch circuits is controlled on the basis of the differential signal which is output from the driver.

9. The semiconductor integrated circuit according to claim 7, further comprising:

a receiver which includes a second inverting input terminal connected to the first inverting input terminal of the squelch circuit and a second noninverting input terminal connected to the first noninverting input terminal of the squelch circuit, and which outputs a signal depending upon amplitude of a differential signal input to the second inverting input terminal and the second noninverting input terminal; and

a deserializer which conducts serial-parallel conversion on the signal output from the receiver and outputs a resultant signal.

11. The semiconductor integrated circuit according to claim 1, wherein on/off of the first to fourth switch circuits are controlled on the basis of a clock signal.

12. The semiconductor integrated circuit according to claim 5, wherein, the first DC voltage is constant and the second DC voltage is constant.

15. The semiconductor integrated circuit according to claim 1, wherein the first switch circuit is connected between the first reception terminal and the first noninverting input terminal,

the second switch circuit is connected between the second reception terminal and the first inverting input terminal,

the third switch circuit is connected between the first reception terminal and the first inverting input terminal, and

the fourth switch circuit is connected between the second reception terminal and the first noninverting input terminal.

16. The semiconductor integrated circuit according to claim 7, wherein the driver and the serializer make up a transmission circuit, an inverting output terminal of the driver being connected to the first transmission terminal, and a noninverting output terminal of the driver being connected to the second transmission terminal 6.

19. The semiconductor integrated circuit according to claim 16, further comprising a multiplexer to which the test pattern signal and a data pattern signal to be transmitted are input, the multiplexer being adapted to output either the test pattern signal or the data pattern signal,

wherein the serializer is adapted to conduct parallel-serial conversion on a signal from the multiplexer and output a resultant signal to the driver.

3. A semiconductor integrated circuit comprising:

a first reception terminal and a second reception terminal receiving a differential signal;

a test terminal applied a DC voltage;

a squelch circuit which has a first noninverting input terminal connected to the first reception terminal and a first inverting input terminal connected to the second reception terminal, which compares differential amplitude between a signal which is input to the first noninverting input terminal and a signal which is input to the first inverting input terminal with a preset threshold, and which outputs a signal depending upon a result of the comparison;

a first switch circuit which brings about conduction between the test terminal and the first noninverting input terminal when it is switched to an on-state, and which brings about insulation between the test terminal and the first noninverting input terminal when it is switched to an off-state;

a second switch circuit which brings about conduction between ground and the first inverting input terminal when it is switched to an on-state, and which brings about insulation between the ground and the first inverting input terminal when it is switched to an off-state;

a third switch circuit which brings about conduction between the test terminal and the first inverting input terminal when it is switched to an on-state, and which brings about insulation between the test terminal and the first inverting input terminal when it is switched to an off-state; and

a fourth switch circuit which brings about conduction between the ground and the first noninverting input terminal when it is switched to an on-state, and which brings about insulation between the ground and the first noninverting input terminal when it is switched to an off-state.

4. The semiconductor integrated circuit according to claim 3,

wherein at time of test operation of the squelch circuit,

in a state in which a DC voltage is applied to the test terminal,

the first switch circuit and the second switch circuit are controlled to be synchronized to each other in on/off and the third switch circuit and the fourth switch circuit are controlled to be synchronized in on/off and be complementary in on/off to the first and second switch circuits.

6. The semiconductor integrated circuit according to claim 4, further comprising a pattern generator which is adapted to generate a test pattern signal,

wherein on/off of the first to fourth switch circuits are controlled on the basis of the test pattern signal.

8. The semiconductor integrated circuit according to claim 6, further comprising:

a serializer which conducts parallel-to-serial conversion on the test pattern signal supplied from the pattern generator and outputs a resultant signal; and

a driver which outputs the signal supplied from the serializer, as a differential signal,

wherein on/off of the first to fourth switch circuits is controlled on the basis of the differential signal which is output from the driver.

10. The semiconductor integrated circuit according to claim 8, further comprising:

a receiver which includes a second inverting input terminal connected to the first inverting input terminal of the squelch circuit and a second noninverting input terminal connected to the first noninverting input terminal of the squelch circuit, and which outputs a signal depending upon amplitude of a differential signal input to the second inverting input terminal and the second noninverting input terminal; and

a deserializer which conducts serial-parallel conversion on the signal output from the receiver and outputs a resultant signal.

13. The semiconductor integrated circuit according to claim 3, wherein on/off of the first to fourth switch circuits are controlled on the basis of a clock signal.

14. The semiconductor integrated circuit according to claim 6, wherein, the first DC voltage is constant and the second DC voltage is constant.

17. The semiconductor integrated circuit according to claim 8, wherein the driver and the serializer make up a transmission circuit, an inverting output terminal of the driver being connected to the first transmission terminal, and a noninverting output terminal of the driver being connected to the second transmission terminal 6.

18. The semiconductor integrated circuit according to claim 3, wherein the first switch circuit is connected between the test terminal and the first noninverting input terminal,

the second switch circuit is connected between the ground and the first inverting input terminal,

the third switch circuit is connected between the test terminal and the first inverting input terminal, and

the fourth switch circuit is connected between the ground and the first noninverting input terminal.

20. The semiconductor integrated circuit according to claim 17, further comprising a multiplexer to which the test pattern signal and a data pattern signal to be transmitted are input, the multiplexer being adapted to output either the test pattern signal or the data pattern signal,

wherein the serializer is adapted to conduct parallel-serial conversion on a signal from the multiplexer and output a resultant signal to the driver.