CIRCUIT AND METHOD OF CLOCKING MULITIPLE DIGITAL CIRCUITS IN MULTIPLE PHASES

• US 20110181325A1
• Filed: 01/27/2010
• Published: 07/28/2011
• Est. Priority Date: 01/27/2010
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Trager, David S., May, Michael Robert
• Granted Patent: US 9,041,452 B2
• Time in Patent Office: Days
• US Class Current: 327/141
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A circuit includes a power supply terminal and a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases. The circuit further includes a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal. Each digital circuit includes an input to receive data and logic to process the data. Each digital circuit is responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the regulated power supply terminal to process the data to produce a data output. Additionally, the circuit includes an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

Claims

1. A circuit comprising:

a power supply terminal;

a clock parsing circuit configured to produce multiple clock signals having a common clock period and different phases;

a plurality of digital circuits coupled to the clock parsing circuit and the power supply terminal, each digital circuit including an input to receive data and logic to process the data, each digital circuit responsive to a phase associated with a respective clock signal of the multiple clock signals to draw current from the power supply terminal to process the data to produce a data output; and

an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

2. The circuit of claim 1, wherein the output timing management circuit comprises a synchronization circuit coupled to each of the plurality of digital circuits and configured to receive an input clock signal, the synchronization circuit configurable to synchronize the output data from each of the multiple digital circuits to the input clock signal to produce a synchronized data output.

3. The circuit of claim 1, further comprising:

a power supply pin; and

a regulator circuit coupled to the power supply pin and configured to receive a power supply current from the power supply pin, the regulator circuit to provide a regulated power supply voltage to the power supply terminal.

4. The circuit of claim 3, wherein each of the plurality of digital circuits draw a substantially similar total current from the regulated power supply terminal in response to a transition of the respective clock signal.

5. The circuit of claim 4, wherein a total instantaneous current drawn by the plurality of digital circuits is substantially constant over the common clock period.

6. The circuit of claim 1, wherein the multiple clock signals comprise an even number of clock signals having a respective number of unique phases within the common clock period.

7. The circuit of claim 1, wherein the output management timing circuit comprises a control circuit configured to control data transfers between each of the plurality of digital circuits and a respective one of the destination circuits.

8. The circuit of claim 1, wherein the output management timing circuit comprises an intermediate clock domain circuit having relaxed input timing constraints and configured to re-clock each of the digital outputs to an intermediate clock frequency.

9. A method comprising:

receiving an input clock signal having a clock period at a clock parsing circuit;

generating multiple phase-shifted output clock signals based on the input clock signal using the clock parsing circuit, each of the multiple phase-shifted output clock signals having a respective phase offset within an output clock period; and

providing the multiple phase-shifted output clock signals to a plurality of digital circuits to drive the plurality of digital circuits in multiple phases, each digital circuit including a data input to receive data;

processing at least a portion of the data at each digital circuit using a unique one of the multiple phase-shifted clock signals to produce a respective data output; and

.

managing each of the respective data outputs of each of the plurality of digital circuits to prevent subsequent timing violations at destination circuits using an output timing management circuit.

10. The method of claim 9, wherein generating the multiple phase-shifted output clock signals comprises:

generating an even number of phase-shifted output clock signals.

11. The method of claim 9, wherein each of the multiple phase-shifted output clock signals has unique phase relative to other phase-shifted output clock signals of the multiple phase-shifted output clock signals.

12. The method of claim 9, wherein providing the multiple phase-shifted output clock signals to the plurality of digital circuits comprises:

driving a first circuit using a first phase-shifted output clock signal of the multiple phase-shifted output clock signals to process first data to produce first output data; and

driving a second circuit using a second phase-shifted output clock signal of the multiple phase-shifted output clock signals to process second data to produce second output data; and

wherein managing each of the respective data outputs comprises;

synchronizing the first output data and the second output data to the input clock signal using the output timing management circuit.

13. The method of claim 9, further comprising:

monitoring the plurality of digital circuits to detect a transition from an idle state to an on state of at least one of the plurality of digital circuits;

dividing the input clock signal to produce an altered output clock signal having an altered output clock period; and

providing the altered output clock signal to the clock parsing circuit.

14. The method of claim 9, wherein the output timing management circuit comprises an intermediate clock domain, and wherein managing each of the respective data outputs comprises re-clocking each of the respective outputs to the intermediate clock domain using the output timing management circuit.

15. The method of claim 9, wherein the output timing management circuit comprises a control circuit, and wherein managing each of the respective data outputs comprises:

controlling data transfers between each of the plurality of digital circuits and a respective one of the destination circuits using the control circuit.

16. A circuit comprising:

a clock input configured to receive an input clock signal having an input clock period;

multiple digital circuits, each of the multiple digital circuits including an input to receive data and logic to process the data to produce output data;

a clock parsing circuit coupled to the clock input and configurable to generate multiple phase-shifted output clock signals based on the input clock signal, each of the multiple phase-shifted output clock signals having a respective phase offset within an output clock period, the clock parsing circuit to drive the multiple digital circuits in multiple phases based on the multiple phase shifted output clock signals to process the data in multiple phases; and

an output timing management circuit coupled to each of the plurality of digital circuits and configured to control data outputs of each of plurality of digital circuits to prevent timing violations at one or more destination circuits.

17. The circuit of claim 16, wherein the clock parsing circuit is configured to divide the output clock period into a plurality of sub-intervals, wherein each of the multiple phase-shifted output clock signals is aligned to a unique one of the plurality of sub-intervals.

18. The circuit of claim 16, wherein the output timing management circuit comprises:

a synchronization circuit coupled to each of the multiple digital circuits and configured to receive the input clock signal, the synchronization circuit configurable to synchronize the output data from each of the multiple digital circuits to the input clock signal to produce a synchronized data output.

19. The circuit of claim 16, wherein the output timing management circuit comprises:

a control circuit coupled to each of the multiple digital circuits and configured to manage routing of the output data from each of the multiple digital circuits to a respective one of the one or more destination circuits.

20. The circuit of claim 16, wherein the output timing management circuit has a an intermediate clock domain and has relaxed input constraints, the output timing management circuit is configured to re-clock the output data from each of the multiple digital circuits to the intermediate clock domain.

21. The circuit of claim 19, further comprising:

a power supply terminal; and

a voltage regulator circuit configured to provide a substantially constant power supply voltage to the power supply terminal;

wherein each of the multiple digital circuits is coupled to the power supply terminal; and

wherein timing of current drawn by the multiple digital circuits in response to the multiple phase-shifted output clock signals is distributed across the output clock period.

22. The circuit of claim 20, further comprising:

a filter circuit coupled to the power supply terminal to filter AC current variations.

23. The circuit of claim 16, further comprising:

a startup circuit configured to adjust a period of the input clock signal during a state transition associated with the multiple digital circuits to control a rate of the state transition.

24. The circuit of claim 16, wherein the multiple digital circuits comprise different clock domains within a digital signal processor.