Stacked linear power amplifier with capacitor feedback and resistor isolation

• US 20110181360A1
• Filed: 01/25/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Li, Yang Edward, Bacon, Peter, Broughton, Robert, Bonkowski, James
• Granted Patent: US 8,487,706 B2
• Time in Patent Office: Days
• US Class Current: 330/277
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/342 in field-effect transistor amplifiers
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 3/423 with MOSFET's

Abstract

A power amplifier with stacked, serially connected, field effect transistors is described. DC control voltage inputs are fed to the gates of each transistor. Capacitors are coupled to the transistors. The inputs and the capacitors are controlled to minimize generation of non-linearities of each field effect transistor and/or to maximize cancellation of distortions between the field effect transistors of the power amplifier in order to improve linearity of the power amplifier output.

Claims

1. A power amplifier circuit comprising:

a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor;

one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors; and

one or more capacitors, each coupled to a respective one of the one or more additional field effect transistors,

wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id.

2. The power amplifier circuit of claim 1, wherein

the first DC control voltage input is coupled to the gate electrode of the first field effect transistor by a first resistor;

the one or more additional DC control voltage inputs are each coupled to the respective gate electrodes of the one or more additional field effect transistors by respective one or more additional resistors; and

the one or more capacitors are each coupled to the respective one of the one or more additional field effect transistors.

3. The power amplifier circuit of claim 2, wherein at least some of the one or more capacitors are coupled to the respective one of the one or more additional field effect transistors by the one or more additional resistors.

4. The power amplifier circuit of claim 2 or 3, wherein the first resistor and the one or more additional resistors are controllable to maximize the cancellation of distortions.

5. The power amplifier circuit of claim 1, wherein minimization of non-linearities and maximization of cancellation of distortions occurs through intermodulation distortion minimization.

6. The power amplifier circuit of claim 5, wherein intermodulation distortion minimization occurs by minimizing third or higher order intermodulation distortion of the power amplifier circuit.

7. The power amplifier circuit of claim 5, wherein intermodulation distortion minimization occurs by minimizing at least one between transconductance, output resistance, gate-to-source capacitance, and gate-to-drain capacitance of the power amplifier circuit.

8. The power amplifier circuit of claim 7, wherein the at least one between transconductance, output resistance, gate-to-source capacitance, and gate-to-drain capacitance is experimentally measured.

9. The power amplifier circuit of claim 1, wherein the first DC control voltage input and the one or more additional DC control voltage inputs are selected to minimize the generation of non-linearities and the one or more capacitors are selected to maximize the cancellation of the distortions.

10. The power amplifier of claim 1, wherein the first DC control voltage input and the one or more additional DC control voltage inputs are selected to maximize the cancellation of the distortions and the one or more capacitors are selected to minimize the generation of non-linearities.

11. The power amplifier circuit of claim 1, wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to jointly minimize the generation of non-linearities and jointly maximize the cancellation of the distortions.

24. The system of claim 21, wherein the power amplifier comprises the power amplifier defined by claim 1.

12. A power amplifier comprising a plurality of amplifying components connected in parallel, each amplifying component comprising:

a) a first field effect transistor wherein a first DC control voltage input is adapted to be coupled to a gate terminal of the first field effect transistor;

b) one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate terminals of the one or more additional field effect transistors; and

c) one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor,

wherein

i) an RF input signal terminal is adapted to be coupled to the gate terminal of the first field effect transistor of each amplifying component, thus providing the power amplifier with the same input to each amplifying component;

ii) an output of the power amplifier is taken on the drain terminal of the last one of the one or more additional field effect transistors of each amplifying component, thus providing the power amplifier with the same output from each amplifying component; and

iii) the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors of at least one amplifying component are selected to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors of the at least one amplifying component are biased with different drain-source voltages Vds, gate-source voltages Vgs and/or drain currents Id.

13. The power amplifier circuit of claim 12, wherein minimization of non-linearities and maximization of cancellation of distortions occurs through intermodulation distortion minimization.

14. The power amplifier circuit of claim 12, wherein the first DC control voltage input and the one or more additional DC control voltage inputs are selected to minimize the generation of non-linearities and the one or more capacitors are selected to maximize the cancellation of the distortions.

15. The power amplifier of claim 12, wherein the first DC control voltage input and the one or more additional DC control voltage inputs are selected to maximize the cancellation of the distortions and the one or more capacitors are selected to minimize the generation of non-linearities.

16. The power amplifier circuit of claim 12, wherein the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors are selected to jointly minimize the generation of non-linearities and jointly maximize the cancellation of the distortions.

25. A system for improving linearity of a power amplifier, comprising:

a sensor;

a bias adjustment arrangement coupled to the sensor;

a bias generator coupled to the bias adjustment arrangement; and

a power amplifier coupled to the bias generator, the power amplifier adapted to receive an input signal and to provide an output signal to a load,

wherein the bias adjustment arrangement controls bias values to be generated by the bias generator and fed to the power amplifier by reducing non-linearity of the output signal of the power amplifier through action on parameters on which the non-linearity of the output signal depends, and

wherein the power amplifier comprises the power amplifier of claim 12.

17. A method for controlling DC voltage inputs and capacitance values of a power amplifier, comprising:

providing a first field effect transistor, wherein i) an RF input signal terminal is adapted to be coupled to a gate electrode of the first field effect transistor and ii) a first DC control voltage input is adapted to be coupled to the gate electrode of the first field effect transistor;

providing one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate electrodes of the one or more additional field effect transistors, an output of the power amplifier circuit being taken on a drain electrode of the last one of the one or more additional field effect transistors;

providing one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor; and

controlling the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier circuit whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id.

18. The method of claim 17, wherein minimization of non-linearities and maximization of cancellation of distortions occurs through intermodulation distortion minimization.

19. A method for controlling DC voltage inputs and capacitance values of a power amplifier, comprising:

a) providing a first field effect transistor, wherein a first DC control voltage input is adapted to be coupled to a gate terminal of the first field effect transistor;

b) providing one or more additional serially connected field effect transistors serially connected among themselves and to the first field effect transistor, each having a source terminal connected to a drain terminal of a preceding field effect transistor, wherein one or more additional DC control voltage inputs are each coupled to respective gate terminals of the one or more additional field effect transistors; and

c) providing one or more capacitors, each coupled to a respective one of the one or more additional field effect transistor, wherein;

i) an RF input signal terminal is adapted to be coupled to the gate terminal of the first field effect transistor of each amplifying component, thus providing the power amplifier with the same input to each amplifying component; and

ii) an output of the power amplifier is taken on the drain terminal of the last one of the one or more additional field effect transistors of each amplifying component, thus providing the power amplifier with the same output from each amplifying component,

the method further comprising

d) controlling the first DC control voltage input, the one or more additional DC control voltage inputs and the one or more capacitors of at least one amplifying component to minimize generation of non-linearities of each field effect transistor of the power amplifier circuit and/or to maximize, through phase alignment, cancellation of distortions between the field effect transistors of the power amplifier whereby, upon minimization of non-linearities and/or maximization of cancellation of distortions, at least two of the first field effect transistor and the one or more additional field effect transistors of the at least one amplifying component are biased with different drain-source voltages Vds, different gate-source voltages Vgs and/or different drain currents Id.

20. The method of claim 19, wherein minimization of non-linearities and maximization of cancellation of distortions occurs through intermodulation distortion minimization.

21. A system for improving linearity of an electronic circuit, comprising:

a sensor;

a bias adjustment arrangement coupled to the sensor;

a bias generator coupled to the bias adjustment arrangement; and

an electronic circuit coupled to the bias generator, the power amplifier adapted to receive an input signal and to provide an output signal to a load,

wherein the bias adjustment arrangement controls bias values to be generated by the bias generator and fed to the electronic circuit to reduce the non-linearity of the output signal of the electronic circuit through action on parameters on which the non-linearity of the output signal depends.

22. The system of claim 21, further comprising a coupler coupled between the electronic circuit and the load, the coupler receiving the output signal of the electronic circuit, and feeding a first coupler output back to the sensor and a second coupler output to the load.

23. The system of claim 21, wherein the electronic circuit is a power amplifier.