Digital Front End In System Simultaneously Receiving GPS And GLONASS Signals

• US 20110181468A1
• Filed: 04/05/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yeh, Wen-Chang, Huang, Justin, Sun, Qinfang
• Granted Patent: US 8,410,979 B2
• Time in Patent Office: Days
• US Class Current: 342/357.73
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/235 Calibration of receiver components
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/33 Multimode operation in different systems which transmit time stamped messages, e.g. GPS/GLONASS
• CPC Class Codes: G01S 19/36 relating to the receiver frond end

Abstract

A receiver for receiving both GPS signals and GLONASS signals is provided. This receiver includes an analog front end (AFE), a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE, and a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs. Search engines are provided for receiving outputs of the DMI. Notably, certain front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals.

Claims

1. A receiver for receiving GPS signals and GLONASS signals, the receiver comprising:

an analog front end (AFE);

a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE;

a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs; and

search engines for receiving outputs of the DMI,

wherein front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals,

wherein the GPS DFE includes;

a low pass filter (LPF) for filtering and decimating the output signal of the AFE; and

a multiplexer for selecting one of the output signal of the AFE and an output signal of the LPF.

2. The receiver of claim 1, wherein the multiplexer selects the output of the LPF when the output signal of the AFE is 64 MHz, and wherein the LPF includes a 2:

1 decimator that generates a 32 MHz signal.

3. The receiver of claim 1, wherein the GPS DFE includes a bandpass filter for filtering out interference from an output signal of the multiplexer, the bandpass filter including programmable coefficients to allow a tradeoff between interference rejection and signal loss.

4. The receiver of claim 1, wherein the GPS DFE includes at least one spur estimation cancellation (SEC) block for cancelling a known spur frequency from the output signal of the multiplexer.

5. The receiver of claim 4, wherein each SEC block includes a numerically-controlled oscillator (NCO) for generating a phase of a spur based on a sample, the sample being a spur frequency/analog-to-digital converter (ADC) frequency.

6. The receiver of claim 5, wherein each SEC further includes a sin/cos table for generating a four quadrant phasor based on the phase provided by the NCO.

7. The receiver of claim 6, wherein each SEC further includes a conjugate multiplier for multiplying a conjugate of the four quadrant phasor and an output signal of the AFE.

8. The receiver of claim 7, wherein each SEC further includes a summation block for averaging results of the conjugate multiplier over a large block size.

9. The receiver of claim 8, wherein each SEC further includes a complex-by-complex multiplier for multiplying a dumped value from the summation block and the four quadrant phasor.

10. The receiver of claim 9, wherein each SEC further includes an adder for adding the output signal of the AFE and a real result of the complex-by-complex multiplier.

11. The receiver of claim 1, wherein the GPS DFE includes a first spur estimation cancellation (SEC) block and a second SEC block, wherein an output signal of the first SEC is in s8.4 format and an output signal of the second SEC is in s6.4 format.

12. The receiver of claim 1, wherein the GPS DFE includes a DC estimation and cancellation block for performing an accumulator function, which is normalized by sample counts.

13. The receiver of claim 12, wherein an output signal of the DEC includes fractional bits to reduce quantization error.

14. The receiver of claim 13, wherein an output signal of the DEC is in s6.4 format.

15. The receiver of claim 1, wherein the GPS DFE includes a digital mixer for converting an intermediate frequency (IF) signal to a baseband signal.

16. The receiver of claim 15, wherein the digital mixer provides a residual frequency offset after converting that is greater than a maximum Doppler frequency.

17. The receiver of claim 15, wherein the digital mixer has a one path 8-bit in, two path (I/Q) out configuration.

18. The receiver of claim 15, wherein the GPS DFE includes an integrate and dump decimation (ID2) block that receives output signals of the digital mixer.

19. The receiver of claim 18, wherein the ID2 block includes a 2:

1 decimator that generates a 16 MHz signal.

20. The receiver of claim 18, wherein the GPS DFE includes a quantizer block that converts output signals of the ID2 block into a sign bit and a magnitude bit.

21. The receiver of claim 20, wherein the quantizer combines the sign and magnitude bits in a two-bit format compatible with legacy devices.

22. The receiver of claim 20, wherein the magnitude bit is compared with a threshold, which is based on parameters including a desired signal power relative to a maximum power at an output of the GPS DFE, and a desired signal power relative to a maximum power at an input of the quantizer.

23. A receiver for receiving GPS signals and GLONASS signals, the receiver comprising:

an analog front end (AFE);

a GPS digital front end (DFE) and a GLONASS DFE for receiving an output of the AFE;

a dual mode interface (DMI) for receiving outputs of the GPS and GLONASS DFEs; and

search engines for receiving outputs of the DMI,

wherein front-end components of the AFE are configured to process both the GPS signals and the GLONASS signals,

wherein the GLONASS DFE includes at least one spur estimation cancellation (SEC) block for cancelling a known spur frequency.

24. The receiver of claim 23, wherein each SEC block includes a numerically-controlled oscillator (NCO) for generating a phase of a spur based on a sample, the sample being a spur frequency/analog-to-digital converter (ADC) frequency.

25. The receiver of claim 24, wherein each SEC further includes a sin/cos table for generating a four quadrant phasor based on the phase provided by the NCO.

26. The receiver of claim 25, wherein each SEC further includes a conjugate multiplier for multiplying a conjugate of the four quadrant phasor and an output signal of the AFE.

27. The receiver of claim 26, wherein each SEC further includes a summation block for averaging results of the mixer over a large block size.

28. The receiver of claim 27, wherein each SEC further includes a complex-by-complex multiplier for multiplying a dumped value from the summation block and the four quadrant phasor.

29. The receiver of claim 28, wherein each SEC further includes an adder for adding the output signal of the AFE and a real result of the complex-by-complex multiplier.

30. The receiver of claim 23, wherein the GLONASS DFE includes a digital mixer for converting an intermediate frequency (IF) signal based on the output of the AFE to a baseband signal.

31. The receiver of claim 30, wherein the digital mixer has a one path 8-bit in, two path (I/Q) out configuration.

32. The receiver of claim 31, wherein the GLONASS DFE includes at least one low pass filter (LPF) for filtering and decimating an output signal of the digital mixer.

33. The receiver of claim 32, wherein each LPF includes a 2:

1 decimator.

34. The receiver of claim 33, wherein the GLONASS DFE includes a quantizer block that converts output signals of a last LPF into a sign bit and a magnitude bit.

35. The receiver of claim 34, wherein the quantizer block combines the sign and magnitude bits in a two-bit format compatible with legacy devices.

36. The receiver of claim 34, wherein the magnitude bit is compared with a threshold, which is based on parameters including a desired signal power relative to a maximum power at an output of the GLONASS DFE, and a desired signal power relative to a maximum power at an input of the quantizer.