DISPLAY DEVICE AND DRIVING METHOD THEREOF

• US 20110181631A1
• Filed: 04/06/2011
• Published: 07/28/2011
• Est. Priority Date: 08/24/2005
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Yamazaki, Shunpei, Shishido, Hideaki
• Application Number:
  US13/080,709
• Publication Number:
  US 20110181631A1
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/204 the sub-frames being organized in consecutive sub-frame groups
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/2077 by a combination of two or more gradation control methods
• CPC Class Codes: G09G 3/3225 using an active matrix

Abstract

A pixel is divided into m (m is an integer of m≧2) sub-pixels, and an area ratio of an s-th (s is an integer of 1 to m) sub-pixel is to be 2^s-1. Also, k (k is an integer of k≧2) sub-frame groups including a plurality of sub-frames are provided in one frame, along with dividing one frame into n (n is an integer of n≧2) sub-frames, so that a ratio of a lighting period length of a t-th (t is an integer of 1 to n) sub-frame is 2^(t-1)m. Further, each of the n sub-frames is divided into k sub-frames each having a lighting period length that is about 1/k of each of the n sub-frames, and one of these is provided in each of the k sub-frame groups.

Claims

1. A display device comprising:

a pixel comprising;

a first EL element;

a second EL element;

a first transistor; and

a second transistor,

wherein an area ratio of a first pixel electrode of the first EL element and a second pixel electrode of the second EL element is 1;

2, and

wherein the first transistor and the second transistor each includes Ga.

2. The display device according to claim 1, wherein the first transistor and the second transistor each includes a-InGaZnO.

3. An electronic device comprising the display device according to claim 1.

4. A display device comprising:

a pixel comprising;

a first EL element;

a second EL element;

a first transistor; and

a second transistor,

wherein an area of a first pixel electrode of the first EL element is smaller than an area of a second pixel electrode of the second EL element, and

wherein the first transistor and the second transistor each includes Ga.

5. The display device according to claim 4, wherein the first transistor and the second transistor each includes a-InGaZnO.

6. An electronic device comprising the display device according to claim 4.

7. A display device comprising:

a pixel comprising;

a first EL element;

a second EL element;

a first transistor; and

a second transistor,

wherein an area ratio of a first pixel electrode of the first EL element and a second pixel electrode of the second EL element is 1;

2, and

wherein the first transistor and the second transistor each includes Ga and In.

8. The display device according to claim 7, wherein the first transistor and the second transistor each includes a-InGaZnO.

9. An electronic device comprising the display device according to claim 7.

10. A display device comprising:

a pixel comprising;

a first EL element;

a second EL element;

a first transistor; and

a second transistor,

wherein an area of a first pixel electrode of the first EL element is smaller than an area of a second pixel electrode of the second EL element, and

wherein the first transistor and the second transistor each includes Ga and Zn.

11. The display device according to claim 10, wherein the first transistor and the second transistor each includes a-InGaZnO.

12. An electronic device comprising the display device according to claim 10.