DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

• US 20110181806A1
• Filed: 01/21/2011
• Published: 07/28/2011
• Est. Priority Date: 01/24/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Granted Patent: US 8,866,984 B2
• Time in Patent Office: Days
• US Class Current: 349/46
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/1336 Illuminating devices
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2360/144 the light being ambient light
• CPC Class Codes: G09G 3/3406 Control of illumination source illumination devices structurally associated with liquid crystal cells G02F1/1336
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/153 in a repetitive configuration, e.g. LED bars
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 : having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.

Claims

1. A liquid crystal display device comprising a pixel, the pixel comprising:

a transistor; and

a liquid crystal element electrically connected to the transistor,

wherein the transistor comprises;

a gate electrode;

a first insulating layer over the gate electrode;

a

an oxide semiconductor layer over the first insulating layer;

a source terminal and a drain terminal over the oxide semiconductor layer; and

a second insulating layer over the source terminal and the drain terminal,

wherein off current of the transistor is lower than 10 zA/μ

m at room temperature.

2. The liquid crystal display device according to claim 1,

wherein the off current of the transistor is lower than 100 zA/μ

m at 85°

C.

3. The liquid crystal display device according to claim 1,

wherein the second insulating layer is in contact with the oxide semiconductor layer in a region between the source terminal and the drain terminal.

4. The liquid crystal display device according to claim 1, further comprising a lighting unit,

wherein the lighting unit comprises a light source, and

wherein the light source is selected from a light-emitting diode and an organic electroluminescence element.

5. The liquid crystal display device according to claim 1,

wherein the oxide semiconductor layer comprises indium, zinc, and a metal which is selected from Ga, Fe, Ni, Mo, and Co.

6. The liquid crystal display device according to claim 1,

wherein the source terminal and the drain terminal comprises a metal nitride.

7. The liquid crystal display device according to claim 1,

wherein the source terminal and the drain terminal comprises tungsten nitride, titanium nitride, or molybdenum nitride.

8. The liquid crystal display device according to claim 1,

wherein a maximum field-effect mobility of the transistor is greater than or equal to 5 cm²/Vsec when the transistor is in an on state.

9. The liquid crystal display device according to claim 1,

wherein a maximum field-effect mobility of the transistor is 10 cm²/Vsec to 150 cm²/Vsec inclusive when the transistor is in an on state.

10. The liquid crystal display device according to claim 1,

wherein the oxide semiconductor layer is an intrinsic semiconductor or a substantially intrinsic semiconductor, and

wherein a channel formation region is formed in the oxide semiconductor layer.