MULTI LAYER CHIP CAPACITOR, AND METHOD AND APPARATUS FOR MANUFACTURING THE SAME

• US 20110181999A1
• Filed: 04/04/2011
• Published: 07/28/2011
• Est. Priority Date: 06/21/2005
• Status: Active Grant

• Current Assignee: Jae-Ho Ha
• Original Assignee: Jae-Ho Ha
• Inventors: HA, Jae-Ho
• Granted Patent: US 8,443,498 B2
• Time in Patent Office: Days
• US Class Current: 361/311
• CPC Class Codes: H01G 13/00 Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/085 Vapour deposited
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/306 made by thin film techniques
• CPC Class Codes: Y10T 29/43 Electric condenser making
• CPC Class Codes: Y10T 29/435 Solid dielectric type
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/5313 Means to assemble electrical device
• CPC Class Codes: Y10T 29/53174 Means to fasten electrical component to wiring board, base, or substrate
• CPC Class Codes: Y10T 29/53178 Chip component

Abstract

The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

Claims

1. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

positioning a dielectric layer deposition source to be perpendicular to a single shadow mask having a plurality of slits and a conductor layer deposition source to be oblique to the single shadow mask; and

forming the dielectric layer and the conductor layer by evaporating evaporated particles from the respective deposition sources to pass through the slits and to be deposited on the substrate.

2. The method of manufacturing a multi-layer chip capacitor according to claim 1, wherein a range of a deposition angle for obliquely positioning the conductor layer deposition source is from 5 degrees to 45 degrees in the direction perpendicular to the shadow mask.

3. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising moving a mask set, in which the shadow mask is mounted, in the height direction based on a layer growth rates of the conductor layer and the dielectric layer during the deposition of the conductor layer and the dielectric layer.

4. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising repeating a control of the shadow mask to be separated from the substrate during the deposition of the conductor layer and the dielectric layer and of precisely adjusting the position of the separated shadow mask upwardly based on growth rates of the deposited layers every predetermined time period.

5. The method of manufacturing a multi-layer chip capacitor according to claim 1, further comprising controlling a mask set to move in the height direction to prevent a deposition layer formed on the substrate from being damaged by the shadow mask after the formation of the deposition layer and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction.

6. The method of manufacturing a multi-layer chip capacitor according to claim 1, wherein a width directional cross-section of the slits of the shadow mask is a parallelogram and a longitudinal cross-section thereof is a trapezoid.

7. The method of manufacturing a multi-layer chip capacitor according to claim 1, wherein a cross-section of the slits of the shadow mask is one of a parallelogram, a parallelogram with a step, a trapezoid, and a trapezoid with a step.

8. A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to claim 1.

9. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

adjusting and setting a distance between a single shadow mask installed to a mask set to be rotated and revolved and having a plurality of slits;

positioning a dielectric layer deposition source to be perpendicular to the single shadow mask and a conductor layer deposition source to be oblique to the single shadow mask; and

forming the dielectric layer and the conductor layer in the vacuum deposition while controlling the mask set to move along the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction).

10. The method of manufacturing a multi-layer chip capacitor according to claim 9, further comprising forming a thermally decomposable releasing layer on the substrate before the setting.

11. The method of manufacturing a multi-layer chip capacitor according to claim 9, further comprising controlling the mask set to move in the height direction to prevent a deposition layer formed on the substrate from being damaged by the shadow mask after the formation of the deposition layer and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction.

12. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

forming slit patterns for forming desired deposition layers by moving upper and lower mask sets which respectively include shadow masks having a plurality of slits and face each other; and

forming the dielectric layer and the conductor layer by evaporating evaporated particles from respective deposition sources to pass through the slit patterns and to be deposited on the substrate.

13. The method of manufacturing a multi-layer chip capacitor according to claim 12, further comprising moving the mask sets, in which the shadow masks are mounted, in the height direction based on a layer growth rates of the conductor layer and the dielectric layer during the deposition of the conductor layer and the dielectric layer.

14. The method of manufacturing a multi-layer chip capacitor according to claim 12, further comprising repeating a control of the shadow masks to be separated from the substrate during the deposition of the conductor layer and the dielectric layer and of precisely adjusting the positions of the separated shadow masks upwardly based on growth rates of the deposited layers every predetermined time period.

15. The method of manufacturing a multi-layer chip capacitor according to claim 12, further comprising controlling the mask sets to move in the height direction to prevent deposition layers formed on the substrate from being damaged by the shadow masks after the formation of the deposition layers and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction.

16. A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to claim 12.

17. A method of manufacturing a multi-layer chip capacitor by depositing a dielectric layer and a conductor layer in the form of multi-layer chip, while a width of the conductor layer is narrower than a width of the dielectric layer, comprising:

adjusting and setting zero points of upper and lower shadow masks that are mounted in upper and lower mask sets to be rotated and revolved and respectively include a plurality of slits, and distances between the upper and lower shadow masks and the substrate;

forming desired slit patterns using the upper and lower shadow masks by relatively moving the upper and lower mask sets; and

forming the dielectric layer and the conductor layer in the vacuum deposition using the slit patterns.

18. The method of manufacturing a multi-layer chip capacitor according to claim 17, further comprising forming a thermally decomposable releasing layer on the substrate before the setting.

19. The method of manufacturing a multi-layer chip capacitor according to claim 17, further comprising controlling the mask sets to move in the height direction to prevent deposition layers formed on the substrate from being damaged by the shadow masks after the formation of the deposition layers and to be spaced apart from the substrate, and to be positioned in the horizontal direction defined as the width direction and the longitudinal direction.

20. A method of manufacturing a multi-layer chip capacitor by the vacuum deposition, the method comprising:

carrying out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source and by controlling positions of the mask set in the X-, Y-, and Z-axes (the X-axis is the width direction, the Y-axis is the longitudinal direction, and the Z-axis is the height direction) to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

21. A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to claim 20.

22. A method of manufacturing a multi-layer chip capacitor by the vacuum deposition, the method comprising:

adjusting slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

23. A multi-layer chip capacitor manufactured by the method of manufacturing the multi-layer chip capacitor according to claim 22.