MEMORY SYSTEM WITH SECTIONAL DATA LINES

• US 20110182105A1
• Filed: 04/04/2011
• Published: 07/28/2011
• Est. Priority Date: 08/25/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Fasoli, Luca, Yan, Tianhong
• Granted Patent: US 8,358,528 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits

Abstract

A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

Claims

1. A non-volatile storage device, comprising:

non-volatile storage elements;

local data lines in communication with the non-volatile storage elements, the local data lines include a first local data line and a second local data line;

a global data line;

a selection circuit connected the global data line, the local data lines and an unselected bit line signal, the selection circuit selectively connects the global data line to one of the local data lines and connects an unselected local data line to the unselected bit line signal; and

control circuitry in communication with the selection circuit and the global data line, the control circuitry programs and reads the non-volatile storage elements.

2. The non-volatile storage device of claim 1, wherein the selection circuit receives a first selection signal, the selection circuit comprises:

a first pair of transistors connected in parallel and a second pair of transistors connected in parallel, the first pair of transistors are connected to the first local data line and the global data line, the second pair of transistors are connected to the second local data line and the global data line;

a first switch, responsive to the first selection signal, for selectively connecting the first local data line to the unselected bit line signal; and

a second switch, responsive to the first selection signal, for selectively connecting the second local data line to the unselected bit line signal.

3. The non-volatile storage device of claim 2, wherein the selection circuit further comprises:

a first logic circuit that receives the first selection signal and a second selection signal, an output of the first logic circuit controls the first pair of transistors; and

a second logic circuit that receives the first selection signal inverted and the second selection signal, an output of the second logic circuit controls the second pair of transistors.

4. The non-volatile storage device of claim 3, wherein

the first switch is responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the unselected bit line signal;

the second switch is responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the unselected bit line signal;

the first pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the respective connected global data line; and

the second pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the respective connected global data line.

5. The non-volatile storage device of claim 2, wherein the selection circuit further comprises:

a third pair of transistors connected in parallel and a fourth pair of transistors connected in parallel, the third pair of transistors are connected to a third local data line and the global data line, the fourth pair of transistors are connected to a fourth local data line and the global data line;

a third switch, responsive to the first selection signal, for selectively connecting the third local data line to the unselected bit line signal; and

a fourth switch, responsive to the first selection signal, for selectively connecting the fourth local data line to the unselected bit line signal.

6. The non-volatile storage device of claim 5, wherein

the first switch is responsive to the first selection signal and a second selection signal for selectively connecting the first local data line to the unselected bit line signal;

the second switch is responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the unselected bit line signal;

the third switch is responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the unselected bit line signal;

the fourth switch is responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the unselected bit line signal;

the first pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the global data line;

the second pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the global data line;

the third pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the global data line; and

the fourth pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the global data line.

7. The non-volatile storage device of claim 1, wherein

the global data line is in a different metal layer than the local data lines.

8. The non-volatile storage device of claim 1, further comprising:

the non-volatile storage elements are reversible resistance-switching elements.

9. The non-volatile storage device of claim 1, wherein

the plurality of non-volatile storage elements are part of a monolithic three dimensional memory array.

10. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements;

a plurality of bit lines connected to the non-volatile storage elements;

a plurality of word lines connected to the non-volatile storage elements;

a plurality of local data lines;

connection circuits for selectively connecting bit lines to local data lines;

a plurality of global data lines;

multiple selection circuits each of which is connected to one of the global data lines, multiple local data lines and a unselected bit line signal, each selection circuit selectively connects a connected global data line to a first local data line of the respective connected multiple local data lines in response to a first selection signal and connects a second local data lines of the respective connected local data lines to the unselected bit line signal in response to the first selection signal; and

control circuitry connected to the selection circuits, word lines and global data lines, the control circuitry programs and reads the non-volatile storage elements.

11. The non-volatile storage device of claim 10, wherein each selection circuit comprises:

a first pair of transistors connected in parallel and a second pair of transistors connected in parallel, the first pair of transistors are connected to the first local data line and the respective connected global data line, the second pair of transistors are connected to the second local data line and the respective connected global data line;

a first switch, responsive to the first selection signal, for selectively connecting the first local data line to the unselected bit line signal; and

a second switch, responsive to the first selection signal, for selectively connecting the second local data line to the unselected bit line signal.

12. The non-volatile storage device of claim 11, wherein each selection circuit further comprises:

a first NAND gate that receives the first selection signal and a second selection signal, an output of the first NAND gate controls the first pair of transistors; and

a second NAND gate that receives the first selection signal inverted and the second selection signal, an output of the second NAND gate controls the second pair of transistors.

13. The non-volatile storage device of claim 12, wherein:

the first switch is responsive to the output of the first NAND gate for selectively connecting the first local data line to the unselected bit line signal;

the second switch is responsive to the output of the second NAND gate for selectively connecting the second local data line to the unselected bit line signal;

the first pair of transistors are responsive to output of the first NAND gate for selectively connecting the first local data line to the respective connected global data line; and

the second pair of transistors are responsive to the output of the second NAND gate for selectively connecting the second local data line to the respective connected global data line.

14. The non-volatile storage device of claim 11, wherein each selection circuit further comprises:

a third pair of transistors connected in parallel and a fourth pair of transistors connected in parallel, the third pair of transistors are connected to a third local data line and the respective connected global data line, the fourth pair of transistors are connected to a fourth local data line and the respective connected global data line;

a third switch, responsive to the first selection signal, for selectively connecting the third local data line to the unselected bit line signal; and

a fourth switch, responsive to the first selection signal, for selectively connecting the fourth local data line to the unselected bit line signal.

15. The non-volatile storage device of claim 14, wherein

the first switch is responsive to the first selection signal and a second selection signal for selectively connecting the first local data line to the unselected bit line signal;

the second switch is responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the unselected bit line signal;

the third switch is responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the unselected bit line signal;

the fourth switch is responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the unselected bit line signal;

the first pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the respective connected global data line;

the second pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the respective connected global data line;

the third pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the respective connected global data line; and

the fourth pair of transistors are responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the respective connected global data line.

16. The non-volatile storage device of claim 10, wherein

the control circuitry provides the unselected bit line signal.

17. The non-volatile storage device of claim 10, wherein

the control circuitry includes unselected bit-line drivers that drive the unselected bit line signal.

18. The non-volatile storage device of claim 10, wherein

the plurality of non-volatile storage elements comprise a monolithic three dimensional memory array with non-volatile storage elements on multiple vertical levels;

and

the word lines and bit lines are on multiple vertical levels.

19. A non-volatile storage device, comprising:

non-volatile storage elements;

local data lines in communication with the non-volatile storage elements, the local data lines include a first local data line, a second local data line, a third local data line and a fourth local data line;

a sense amplifier;

a global data line in communication with the sense amplifier;

an unselected signal line;

a first selection signal and a second selection signal;

a first switch that is responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the unselected signal line;

a second switch that is responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the unselected signal line;

a third switch that is responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the unselected signal line;

a fourth switch that is responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the unselected signal line;

a first pair of transistors that are responsive to the first selection signal and the second selection signal for selectively connecting the first local data line to the global data line;

a second pair of transistors that are responsive to the first selection signal and the second selection signal for selectively connecting the second local data line to the global data line;

a third pair of transistors that are responsive to the first selection signal and the second selection signal for selectively connecting the third local data line to the global data line; and

a fourth pair of transistors that are responsive to the first selection signal and the second selection signal for selectively connecting the fourth local data line to the global data line.

20. The non-volatile storage device of claim 19, wherein

the plurality of non-volatile storage elements are part of a monolithic three dimensional memory array.

21. The non-volatile storage device of claim 19, further comprising:

bit lines connected to the non-volatile storage elements; and

selection circuits connected to the local data lines and the bit lines.