SOI DEVICE HAVING A SUBSTRATE DIODE WITH PROCESS TOLERANT CONFIGURATION AND METHOD OF FORMING THE SOI DEVICE

• US 20110183477A1
• Filed: 04/07/2011
• Published: 07/28/2011
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hoentschel, Jan, Gehring, Andreas, Wei, Andy
• Granted Patent: US 8,377,761 B2
• Time in Patent Office: Days
• US Class Current: 438/153
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Claims

1-8. -8. (canceled)

9. A method, comprising:

forming a spacer layer in a first opening located in a first device region of an SOI substrate and above a first transistor formed in a second device region, said first opening extending through a buried insulating layer to a crystalline substrate material;

forming a first spacer element on a portion of sidewalls of said first opening while removing said spacer layer from above said first transistor; and

forming a metal silicide in said first transistor and said crystalline substrate material exposed by said first opening having said first spacer element.

10. The method of claim 9, further comprising forming a first doped region in said crystalline substrate material exposed by said first opening prior to forming said first spacer element.

11. The method of claim 10, wherein said first doped region and drain and source regions of said first transistor are formed in a common implantation process.

12. The method of claim 11, further comprising forming a sidewall spacer structure on sidewalls of a gate electrode of said first transistor prior to forming said first opening.

13. The method of claim 9, further comprising removing a sidewall spacer formed on sidewalls of a gate electrode of said first transistor prior to forming said metal silicide.

14. The method of claim 9, wherein said sidewall spacer of said gate electrode is removed prior to forming said spacer layer.

15. The method of claim 9, further comprising forming a second opening in said first device region and a second transistor in said second device region prior to forming said spacer layer, said second transistor representing a transistor of a conductivity type other than said first transistor, said method further comprising forming a second doped region in said crystalline substrate material exposed by said second opening and drain and source regions of said second transistor in a common implantation process.

16. The method of claim 9, further comprising forming a first stress-inducing layer above said first transistor and a second stress-inducing layer above said second transistor after forming said metal silicide, said first and second stress-inducing layers having different types of intrinsic stress.

21. The method of claim 9, further comprising:

forming an etch stop layer above said first transistor and lining said first opening prior to forming said spacer layer; and

removing said spacer layer from above said first transistor using said etch stop layer.

22. The method of claim 10, further comprising forming a second spacer element on said sidewalls of said opening and a third spacer element on sidewalls of a gate electrode of said first transistor prior to forming said spacer layer, wherein said first doped region is formed in the presence of said second spacer element.

23. The method of claim 10, further comprising forming a second doped region in said crystalline substrate material exposed by said first opening using said first spacer element as an implantation mask.

24. The method of claim 23, wherein said first doped region and drain and source regions of said first transistor are formed in a first common implantation process, and the method further comprises forming said second doped region and a second portion of said drain and source regions in a second common implantation.

25. The method of claim 9, further comprising forming extension regions of said first transistor prior to forming said first opening.

26. The method of claim 12, further comprising:

forming extension regions of said first transistor prior to forming said first opening; and

forming said sidewall spacer structure on said sidewalls of said gate electrode after forming said extension regions.

27. The method of claim 9, further comprising forming extension regions of said first transistor and a first doped region in said crystalline substrate material exposed by said first opening prior in a first common implantation process.

28. The method of claim 27, further comprising forming a second doped region in said crystalline substrate material exposed by said first opening after forming said first spacer element.

29. The method of claim 28, further comprising forming a first portion of drain and source regions of said first transistor and said second doped region in a second common implantation process.

30. The method of claim 29, further comprising forming a sidewall spacer structure on sidewalls of a gate electrode of said first transistor prior to forming said first portion of drain and source regions.

31. The method of claim 30, further comprising forming a third doped region in said crystalline substrate material exposed by said first opening in the presence of said sidewall spacer structure prior to forming said first spacer element.

32. The method of claim 31, further comprising forming said third doped region and a second portion of said drain and source regions in a third common implantation process prior to said second common implantation process.

17-20. -20. (canceled)