Asynchronous computer communication

• US 20110185088A1
• Filed: 03/04/2011
• Published: 07/28/2011
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Array Portfolio LLC
• Original Assignee: Array Portfolio LLC
• Inventors: Moore, Charles H.
• Granted Patent: US 8,825,924 B2
• Time in Patent Office: Days
• US Class Current: 710/31
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46

Abstract

A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. A plurality of read lines (18), write lines (20) and data lines (22) interconnect the computers (12). When one computer (12) sets a read line (18) high and the other computer sets a corresponding write line (20) then data is transferred on the data lines (22). When both the read line (18) and corresponding write line (20) go low this allows both communicating computers (12) to know that the communication is completed. An acknowledge line (72) goes high to restart the computers (12).

Claims

1. A computer array, comprising:

a plurality of computers, each of said computers including a processor for executing instructions and a memory; and

a plurality of bidirectional data paths connecting said computers, each of said data paths dedicated between a pair of said computers and including a read line, a write line, and a plurality of data lines; and

wherein

one of said data paths connects a first computer and a second computer;

said first computer indicates its readiness to communicate with said second computer by asserting a first signal on one of said read line and said write line of said data path connecting said first computer and said second computer;

said second computer indicates its readiness to communicate with said first computer by asserting a second signal on the other of said read line and said write line;

when said first computer and said second computer have asserted said first signal and said second signal, then data is transferred between said first computer and said second computer via said data lines of said data path connecting said first computer and said second computer;

when said data is transferred between said first computer and said second computer, then said first signal and said second signal change; and

the changing of said first signal and said second signal is an acknowledgement to at least one of said first computer and said second computer that said data has been successfully transferred between said first computer and said second computer.

2. A computer array according to claim 1, wherein:

said first computer indicates its readiness to communicate by asserting a logical high signal on one of said write line and said read line; and

said second computer indicates its readiness to communicate by asserting a logical high signal on the other of said write line and said read line.

3. A computer array according to claim 2, wherein when said data is transferred between said first computer and said second computer, then said read line and said write line both go low.

4. A computer array according to claim 1, wherein said first computer indicates a readiness to write said data to said second computer by asserting said first signal on said write line.

5. A computer array according to claim 4, wherein said second computer indicates a readiness to read said data from said first computer by asserting said second signal on said read line.

6. A computer array according to claim 5, wherein:

after said first signal and said second signal are asserted, said first computer releases said write line; and

said second computer causes said first signal and said second signal to change.

7. A computer array according to claim 1, wherein:

after said first signal and said second signal are asserted, said first computer and said second computer release said read line and said write line; and

the reading one of said first computer and said second computer causes said first signal and said second signal to change.

8. A computer array according to claim 1, wherein the direction of data transfer between said first computer and said second computer is determined by programs executed by said first computer and said second computer.

9. A computer array according to claim 1, wherein:

each of said computers includes its own sequencer, said sequencer being responsive to input from at least one of an instruction word and said acknowledgement and operative to selectively produce a timing pulse for causing the execution of a subsequent instruction by the computer associated with said sequencer; and

when said first computer indicates its readiness to communicate with said second computer, then said first computer stops operation by suspending the triggering of said timing pulse from said sequencer of said first computer.

10. A computer array according to claim 9, wherein when said second computer indicates its readiness to communicate with said first computer, then said second computer stops operation by suspending the triggering of said timing pulse from said sequencer of said second computer.

11. A computer array according to claim 10, wherein when said first signal and said second signal change, then said acknowledgement triggers said sequencer of said first computer and said sequencer of said second computer to produce another said timing pulse such that said first computer and said second computer resume operation.

12. A computer array according to claim 9, wherein:

said sequencer is automatically suspended from triggering another said timing pulse when said processing unit executes one of a read instruction and a write instruction;

said read instruction causes said first computer to indicate its readiness to read from said second computer; and

a write instruction causes said first computer to indicate its readiness to write to said second computer.

13. A computer array according to claim 1, wherein said plurality of computers is integrated on a single die.

14. A computer array according to claim 1, wherein said first computer is configured to simultaneously indicate its readiness to communicate with said second computer and at least one other computer.

15. A method for communicating between a first computer and a second computer connected via a dedicated data path therebetween, said data path including a read line, a write line, and a plurality of data lines, said method comprising:

causing said first computer to indicate its readiness to communicate with said second computer by asserting a first signal on one of said read line and said write line;

causing said second computer to indicate its readiness to complete a communication with said first computer by asserting a second signal on the other of said read line and said write line;

transferring data between said first computer and said second computer via said plurality of data lines when said first computer and said second computer have indicated their readiness to communicate; and

causing one of said first computer and said second computer to generate an acknowledgement to the other of said first computer and said second computer that said data has been transferred by changing the values of said first signal and said second signal.

16. A method according to claim 15, wherein:

said step of causing said first computer to indicate its readiness to communicate includes causing said first computer to assert a logical high signal on one of said write line and said read line; and

said step of causing said second computer to indicate its readiness to complete said communication includes causing said second computer to assert a logical high signal on the other of said write line and said read line.

17. A method according to claim 16, wherein said step of causing one of said first computer and said second computer to generate said acknowledgement includes causing said one of said first computer and said second computer to cause a logical low signal to be asserted on said read line and said write line.

18. A method according to claim 15, wherein said step of causing said first computer to indicate its readiness to communicate includes causing said first computer to indicate its readiness to write said data to said second computer by asserting said first signal on said write line.

19. A method according to claim 18, wherein said step of causing said second computer to indicate its readiness to complete said communication includes causing said second computer to indicate its readiness to read said data from said first computer by asserting said second signal on said read line.

20. A method according to claim 19, further comprising:

causing said first computer to release said write line after said first signal and said second signal are asserted; and

wherein

said second computer causes said first signal and said second signal to change.

21. A method according to claim 15, further comprising:

causing said first computer and said second computer to release said read line and said write line after said first signal and said second signal have been asserted; and

wherein

said step of causing one of said first computer and said second computer to generate an acknowledgement includes causing the reading one of said first computer and said second computer to cause said first signal and said second signal to change.

22. A method according to claim 15, wherein the direction of data transfer between said first computer and said second computer is determined by programs executed by said first computer and said second computer.

23. A method according to claim 15, wherein:

each of said first computer and said second computer includes its own sequencer, said sequencer being responsive to input from at least one of an instruction word and said acknowledgement and operative to selectively produce a timing pulse for causing the execution of a subsequent instruction by the computer associated with said sequencer; and

when said first computer indicates its readiness to communicate with said second computer, then said first computer stops operation by suspending the triggering of said timing pulse from said sequencer of said first computer.

24. A method according to claim 23, wherein when said second computer indicates its readiness to communicate with said first computer, then said second computer stops operation by suspending the triggering of said timing pulse from said sequencer of said second computer.

25. A method according to claim 24, wherein when said first signal and said second signal change, then said acknowledgement triggers said sequencer of said first computer and said sequencer of said second computer to produce another said timing pulse such that said first computer and said second computer resume operation.

26. A method according to claim 23, wherein:

said sequencer is automatically suspended from triggering another said timing pulse when said processing unit executes one of a read instruction and a write instruction;

said read instruction causes said first computer to indicate its readiness to read from said second computer; and

a write instruction causes said first computer to indicate its readiness to write to said second computer.

27. A method according to claim 15, wherein said first computer and said second computer are integrated on a single die.

28. A method according to claim 15, further comprising causing said first computer to simultaneously indicate its readiness to communicate with said second computer and at least one other computer.

29. A computer array, comprising:

a plurality of computers, each of said computers including a processor for executing instructions and a memory;

a plurality of bidirectional data paths connecting said computers, each of said data paths dedicated between a pair of said computers and including a read line, a write line, and a plurality of data lines;

means for causing said first computer to indicate its readiness to communicate with said second computer via one of said read line and said write line;

means for causing said second computer to indicate its readiness to complete a communication with said first computer by via the other of said read line and said write line;

means for transferring data between said first computer and said second computer when said first computer and said second computer have indicated their readiness to communicate; and

means for acknowledging to at least one of said first computer and said second computer that said communication has been completed, said acknowledgment occurring via at least one of said read line and said write line.