SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM

• US 20110185101A1
• Filed: 03/30/2011
• Published: 07/28/2011
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Borkar, Nitin Y., Wang, Wen-Hann, Cheng, Kai, Pierce, Paul R., Rankin, Linda J., Dermer, Gregory E., Hofsheier, Richard H.
• Granted Patent: US 8,255,605 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Claims

1. A multiprocessor system comprising:

at least one processing module;

at least one input/output module; and

an interconnect network to connect the at least one processing module with the at least one input/output module, the interconnect network comprising;

at least two bridges to send and receive transactions from the input/output modules and the processing module; and

at least two crossbar switches to routes the transactions over a bus between the at least two bridges.

2. The multiprocessor system of claim 1 wherein the at least two bridges support a point-to-point protocol.

3. The multiprocessor system of claim 2 wherein the at least two bridges manage the translation of the point-to-point protocol to a protocol of the interconnect network.

4. The multiprocessor system of claim 1 wherein the at least two crossbar switches are multi-ported non-blocking switches.

6. The multiprocessor system of claim 1 wherein a clock for the at least two crossbar switches has a source that is independent of a clock for the processing modules.

7. The multiprocessor system of claim 1 wherein each processing module comprises at least one processor, a memory and a memory controller.

8. The multiprocessor system of claim 7 wherein each processing module includes four processors.

14. The multiprocessor system of claim 1 wherein each processing module comprises at least one processor, a memory and a memory controller.

5. The multiprocessor system of 1 wherein the at least two crossbar switches support independent power/on and reset of the ports.

9. A multiprocessor system, comprising:

at least one processing module;

at least one input/output module;

one or more buses to communicatively couple the processing modules and the input/output modules;

at least one interconnect component coupled to each one of the processing modules and the input/output modules, the interconnect component to support the protocol of the buses between the processing modules and the input/output modules.

10. The multiprocessor system of claim 9 wherein the interconnect component is included in each one of the processing modules.

11. The multiprocessor system of claim 9 wherein the interconnect component is included in each one of the input/output modules.

12. The multiprocessor system of claim 9 wherein the interconnect component comprises at least one bridge and a crossbar router.

13. The multiprocessor system of claim 9 wherein the interconnect component manages the translation of a point-to-point protocol to a protocol of the one or more buses.

15. A integrated circuit comprising:

a crossbar router; and

a bridge communicatively coupled to the crossbar router, the bridge to packetize transactions between a processing module and in input/output module in a format that is compatible with the crossbar router.

16. The integrated circuit of claim 16 further comprising a plurality of mapping registers communicatively coupled to the bridge, the mapping registers to provide routing information for the bridge.

17. The integrated circuit of claim 16 further comprising at least one DMA engine coupled to the cross bar router, the DMA engine to facilitate message passing between processing modules.