METHOD AND APPARATUS FOR POWER CONTROL

• US 20110185203A1
• Filed: 01/28/2010
• Published: 07/28/2011
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Haider, Amer, Kessler, Richard E., Carlson, David A.
• Granted Patent: US 8,356,194 B2
• Time in Patent Office: Days
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

Claims

1. A method for controlling power in a computer chip, the method comprising:

accumulating power information relating to power consumed during issuing instructions;

comparing accumulated power information against a predetermined threshold; and

preventing further instructions from being issued to reduce power consumption in the computer chip, in an event the accumulated power information exceeds the predetermined threshold.

2. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions over a predetermined time interval.

3. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions as a function of estimating power associated with each issued instruction.

4. The method of claim 3 further including estimating the power associated with each issued instruction as a function of employing a database of power values associated with known instructions.

5. The method of claim 3 further including estimating the power associated with each issued instruction as a function of determining a number of clock cycles elapsed in processing of the instruction.

6. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions over one or more instruction cycles.

7. The method of claim 6 further including preventing further instructions from being issued until one or more instruction cycles have elapsed.

8. The method of claim 6 further including preventing further instructions from being issued until a current throttle period is completed.

9. The method of claim 6 further including preventing further instructions from being issued until a predetermined number of instruction cycles have elapsed.

10. The method of claim 1 further including preventing further instructions from being issued until a predetermined time interval has elapsed.

11. The method of claim 1 further including determining the predetermined threshold as a function of a maximum power allowed in the computer chip.

13. The method of claim 1 further including determining power consumed after preventing further instructions from being issued and adding the consumed power to accumulated power of a subsequent instruction cycle.

12. The method of 1 further including determining the predetermined threshold as a function of one or more chip fuses.

14. A processor comprising:

a power accumulator unit configured to accumulate power information relating to power consumed during issuing instructions;

a comparison unit configured to compare accumulated power information against a predetermined threshold; and

a controller unit configured to block further instructions from being issued to reduce power consumption, in an event the accumulated power information exceeds the predetermined threshold.

15. The processor of claim 14 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions over a predetermined time interval.

16. The processor of claim 14 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions as a function of estimating power associated with each issued instruction.

17. The processor of claim 16 further including a power estimator unit configured to estimate the power associated with each issued instruction as a function of employing a database of power values associated with known instructions.

18. The processor of claim 14 further including a power estimator unit configured to estimate the power associated with each issued instruction as a function of determining a number of clock cycles elapsed in processing of the instruction.

19. The processor of claim 14 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions over one or more instruction cycles.

20. The processor of claim 19 wherein the controller unit is configured to prevent further instructions from being issued until one or more instruction cycles have elapsed.

21. The processor of claim 19 wherein the controller unit is configured to prevent further instructions from being issued until a current throttle period is completed.

22. The processor of claim 19 wherein the controller unit is configured to prevent further instructions from being issued until a predetermined number of instruction cycles have elapsed.

23. The processor of claim 14 wherein the controller unit is configured to prevent further instructions from being issued until a predetermined time interval has elapsed.

24. The processor of claim 14 further wherein the comparison unit is configured to determine the predetermined threshold as a function of a maximum power allowed in the computer chip.

25. The processor of claim 14 further wherein the comparison unit is configured to determine the predetermined threshold as a function of one or more chip fuses.

26. The processor of claim 14 further including an overshoot power estimator configured to estimate power consumed after preventing further instructions from being issued, the consumed power being added to accumulated power of a subsequent instruction cycle.

27. A method for controlling power in a processor, the method comprising:

estimating power consumed by the processor during processing of one or more events; and

preventing further processing in the processor as a function of estimated power to reduce power consumption.

28. The method of claim 27 further including estimating power consumed by the processor as a function of a current flowing into the processor.

29. The method of claim 27 further including estimating power consumed by the processor as a function of a switched capacitance created at the processor by each of the one or more events.

30. The method of claim 27 further including accumulating the power estimates over at least one of a predetermined interval of time or a predetermined number of event cycles.

31. The method of claim 30 further including preventing further processing in the processor if accumulated power exceeds a predetermined threshold.

32. The method of claim 30 wherein the one or more events include at least one of an instruction issued by the processor over an event cycle, a conditional clock enabled over the event cycle, and a cache accessed over the event cycle.

33. The method of claim 27 further including preventing further processing as a function of issuing a throttle signal to a queue or issue pipeline of the processor.

34. The method of claim 27 further including estimating power consumed after preventing further processing.

35. The method of claim 34 further including preventing further processing of an event in the processor as a function of the estimated power of the event and the power consumed after preventing further processing in a preceding event.

36. A processor comprising:

a power estimator configured to estimate power consumed by the processor during processing of one or more events; and

a power controller configured to prevent further processing in the processor as a function of estimated power to reduce power consumption.

37. The processor of claim 36 wherein the power estimator is configured to estimate the power consumed by the processor as a function of a current flowing into the processor.

38. The processor of claim 36 wherein the power estimator is configured to estimate the power consumed by the processor as a function of a switched capacitance created at the processor by each of the one or more events.

39. The processor of claim 36 further including a power accumulator that accumulates the power estimates over at least one of a predetermined interval of time or a predetermined number of event cycles.

40. The processor of claim 39 wherein the power controller is configured to prevent further processing in the processor if accumulated power exceeds a predetermined threshold.

41. The processor of claim 39 wherein the one or more events include at least one of an instruction issued by the processor over an event cycle, a conditional clock enabled over the event cycle, and a cache accessed over the event cycle.

42. The processor of claim 36 wherein the power controller is configured to prevent further processing as a function of issuing a throttle signal to a queue or issue pipeline of the processor.

43. The processor of claim 36 further including an overshoot power estimator configured to estimate power consumed after preventing further processing.

44. The processor of claim 43 wherein the power controller is configured to prevent further processing of an event in the processor as a function of the estimated power of the event and the power consumed after preventing further processing in a preceding event.

45. A method for controlling power consumption, the method comprising:

accumulating information relating to power consumed in a unit during execution of one or more tasks; and

controlling power consumption in the unit by preventing further execution of the one or more tasks in an event the accumulated power information exceeds a predetermined threshold.

46. The method of claim 45 further including accumulating the power information as a function of estimating power consumed during execution of each task.

47. The method of claim 46 further including estimating the power consumed as a function of a database of known power values associated with each task.

48. The method of claim 45 further including accumulating the power information in the unit over at least one of a predetermined interval of time or a predetermined number of tasks.

49. The method of claim 45 further including preventing further execution of the one or more tasks as a function of issuing a throttle signal to an execution pipeline of the unit.

50. The method of claim 45 further including accumulating information relating to power consumed after preventing further execution of the one or more tasks.

51. The method of claim 50 further including preventing further execution of the one or more tasks if a combination of the accumulated power information and consumed power information exceeds the predetermined threshold.

52. An apparatus for controlling power consumption, the apparatus comprising:

a power accumulator to accumulate power information relating to power consumed in a unit during execution of one or more tasks; and

a power controller to control power consumption in the unit by preventing further execution of the one or more tasks in an event the accumulated power information exceeds a predetermined threshold.

53. The apparatus of claim 52 wherein the power accumulator is arranged to accumulate the power information as a function of estimating power consumed during execution of each task.

54. The apparatus of claim 53 wherein the power accumulator includes a power estimator arranged to estimate the power consumed as a function of a database of known power values associated with each task.

55. The apparatus of claim 52 wherein the power accumulator is arranged to accumulate the power information in the unit over at least one of a predetermined interval of time or a predetermined number of tasks.

56. The apparatus of claim 52 wherein the power controller is arranged to prevent further execution of the one or more tasks as a function of issuing a throttle signal to an execution pipeline of the unit.

57. The apparatus of claim 52 wherein the power accumulator is arranged to further accumulate power information relating to power consumed after preventing further execution of the one or more tasks.

58. The apparatus of claim 52 wherein the power controller is arranged to prevent further execution of the one or more tasks if a combination of the accumulated power information and consumed power information exceeds the predetermined threshold.

59. A method for controlling temperature in a computer chip, the method comprising:

monitoring temperature of the chip;

preventing events from being processed in the chip to reduce temperature of the chip, in an event the temperature exceeds a predetermined threshold.

60. The method of claim 59 further including monitoring the temperature of the chip as a function of monitoring a junction temperature of the chip.

61. An apparatus for controlling temperature in a computer chip, the apparatus comprising:

a temperature monitor module to monitor temperature of the chip;

a performance reduction module to prevent events from being processed in the chip to reduce temperature of the chip, in an event the temperature exceeds a predetermined threshold.

62. The apparatus of claim 61 wherein the temperature monitor module monitors the temperature of the chip as a function of monitoring a junction temperature of the chip.