PCMCIA MEMORY CARD WITH ETHERNET/WIRELESS CONNECTIVITY AND BATTERY BACKUP FOR AVIONICS APPLICATIONS

• US 20110185207A1
• Filed: 01/25/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: R.S, Hemanth, Manickam, Balamurugan, Anandappan, Thanga
• Granted Patent: US 8,539,217 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 2213/3804 Memory card connected to a computer port directly or by means of a reader/writer
• CPC Class Codes: G06F 2213/3854 Control is performed at the peripheral side

Abstract

A method to facilitate data transfer to a line replaceable unit that lacks a transmission control protocol/Internet protocol (TCP/IP) interface is provided. The method comprises interfacing a memory-processing card to the line replaceable unit. The memory-processing card includes a memory, a central processing unit module, an interface to the line replaceable unit, an interface to an access point communicatively coupled to the central processing unit module, and a bus arbitrator communicatively coupled to the memory, the central processing unit module, and the interfaces. The method also includes determining a state of the line replaceable unit at the bus arbitrator responsive to the interfacing, providing access at the bus arbitrator from the central processing unit module to the memory when the determined state of the line replaceable unit is OFF, and providing access at the bus arbitrator from the line replaceable unit to the memory when the determined state of the line replaceable unit is ON.

Claims

1. A method to facilitate data transfer to a line replaceable unit that lacks a transmission control protocol/Internet protocol (TCP/IP) interface, the method comprising:

interfacing a memory-processing card to the line replaceable unit, the memory-processing card including;

a memory,

a central processing unit module,

an interface to the line replaceable unit,

an external-card interface to an access point communicatively coupled to the central processing unit module, and

a bus arbitrator communicatively coupled to the memory, the central processing unit module, and the interfaces;

determining a state of the line replaceable unit at the bus arbitrator responsive to the interfacing;

providing access at the bus arbitrator from the central processing unit module to the memory when the determined state of the line replaceable unit is OFF; and

providing access at the bus arbitrator from the line replaceable unit to the memory when the determined state of the line replaceable unit is ON.

2. The method of claim 1, further comprising:

charging a battery in the memory-processing card via the interface to the line replaceable unit when the determined state of the line replaceable unit is ON; and

powering the central processing unit module from the battery in the memory-processing card when the determined state of the line replaceable unit is OFF.

3. The method of claim 1, wherein providing access at the bus arbitrator from the central processing unit module to the memory comprises transitioning the central processing unit module to HIBERNATION mode.

4. The method of claim 3, wherein transitioning the central processing unit module to HIBERNATION mode comprises:

switching off all circuits in the central processing unit module except for a receiver in the central processing unit module; and

waiting to receive a WAKE UP signal sent from an access point at the receiver in the central processing unit module.

5. The method of claim 4, further comprising:

transitioning the central processing unit module to ACTIVE mode when a WAKE UP signal is received at the receiver.

6. The method of claim 5, further comprising:

communicatively coupling the central processing unit module to a remote server via the access point responsive to receiving the WAKE UP signal; and

downloading data to the memory from the remote server via the access point.

7. The method of claim 6, further comprising:

sending a SLEEP signal from the access point to the central processing unit module responsive to completing the downloading of data from the remote server; and

transitioning the central processing unit module to HIBERNATION mode responsive to receiving the SLEEP signal from the access point if the line replaceable unit is still in the OFF state.

8. The method of claim 1, further comprising:

shutting down the central processing unit module when the line replaceable unit is powered up, wherein the central processing unit module is unable to accept signals.

9. The method of claim 1, wherein providing access at the bus arbitrator from the line replaceable unit to the memory when the determined state of the line replaceable unit is ON comprises shutting down the central processing unit module, wherein the central processing unit module is unable to accept signals from the external-card interface to the access point.

10. A memory-processing card for transferring data from a remote unit to a computing device that lacks a transmission control protocol/Internet protocol (TCP/IP) interface, the memory-processing card comprising:

an external-card interface to an access point;

a bus arbitrator to determine a state of the computing device;

a memory communicatively coupled to the bus arbitrator;

a central processing unit module communicatively coupled to the external-card interface, wherein the central processing unit module has access via the bus arbitrator to the memory when a determined state of the computing device is OFF; and

a computing-device interface configured to mate with an interface in the computing device, wherein the computing device has access to the memory when a determined state of the computing device is ON.

11. The memory-processing card of claim 10, further comprising a battery wherein the battery is charged via the computing-device interface when the determined state of the computing device is ON, and wherein the central processing unit module is powered from the battery when the determined state of the computing device is OFF.

12. The memory-processing card of claim 10, wherein the external-card interface includes at least one of a WiFi port and an Ethernet port.

13. The memory-processing card of claim 10, wherein the CPU module includes,

software configured for transmission control protocol/Internet protocol, and

a receiver to receive a WAKE UP signal when the central processing unit module is in a HIBERNATION mode.

14. The memory-processing card of claim 10, wherein the computing device is a line replaceable unit in an aircraft.

15. The memory-processing card of claim 10, wherein the computing-device interface is a personal computer memory card international association (PCMCIA) interface.

16. A system to facilitate data transfer to a line replaceable unit that lacks a transmission control protocol/Internet protocol interface, the system comprising:

the line replaceable unit;

a memory-processing card communicatively coupled to the line replaceable unit; and

an access point communicatively coupled to the memory-processing card, wherein data from a remote server is downloaded to the memory-processing card when the line replaceable unit is powered down.

17. The system of claim 16, wherein the memory-processing card comprises:

an external-card interface to the access point;

a bus arbitrator to determine a state of the line replaceable unit;

a memory communicatively coupled to the bus arbitrator;

a central processing unit module communicatively coupled to the external-card interface, wherein the central processing unit module has access via the bus arbitrator to the memory when a determined state of the line replaceable unit is OFF; and

a line-replaceable-unit interface configured to mate with an interface in the line replaceable unit, wherein the line replaceable unit has access to the memory when a determined state of the line replaceable unit is ON.

18. The memory-processing card of claim 17, wherein the external-card interface includes at least one of a WiFi port and an Ethernet port.

19. The system of claim 17, wherein the memory-processing card further comprises a battery wherein the battery is charged via the line-replaceable-unit interface when the determined state of the line replaceable unit is ON, and wherein the central processing unit module is powered from the battery when the determined state of the line replaceable unit is OFF.

20. The memory-processing card of claim 17, wherein the CPU module includes,

software configured for transmission control protocol/Internet protocol, and

a receiver to receive a WAKE UP signal when the central processing unit module is in a HIBERNATION mode.