Time Synchronization Method and System for Multicore System

• US 20110185216A1
• Filed: 08/27/2009
• Published: 07/28/2011
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: ZTE Corporation
• Original Assignee: ZTE Corporation
• Inventors: Zhao, Yang, Xiao, Li
• Granted Patent: US 8,880,927 B2
• Time in Patent Office: Days
• US Class Current: 713/401
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock

Abstract

A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively allocating each core to each clock synchronization domain; selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization source in the clock synchronization domain, and selecting the clock synchronization domain having the master clock synchronization source with a lowest load as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains; the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value; when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity and releasing to each slave clock synchronization domain, making adjustment based on its time adjustment quantity.

Claims

1. A time synchronization method for a multi-core system, comprising the following steps of:

A, establishing at least one clock synchronization domain, and respectively allocating each core of the multi-core system to each clock synchronization domain;

B, selecting a core with a lowest load in each clock synchronization domain as a master clock synchronization device in the clock synchronization domain, and other cores as slave clock synchronization devices in the clock synchronization domain;

selecting the clock synchronization domain having the master clock synchronization device with a lowest load among various master clock synchronization devices as a master clock synchronization domain, while other clock synchronization domains as slave clock synchronization domains;

C, the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain;

D, when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity of each slave clock synchronization domain and releasing the time adjustment value to each slave clock synchronization domain, and each slave clock synchronization domain making adjustment based on the time adjustment quantity thereof, thereby completing clock synchronization.

2. The time synchronization method according to claim 1, wherein, said step B further comprises the following steps of:

selecting a core with a second lowest load in each clock synchronization domain as a standby clock synchronization device in the clock synchronization domain, and when a core load of the master clock synchronization device is higher than that of the standby clock synchronization device or the master clock synchronization device is abnormal, switching the master clock synchronization device with the standby clock synchronization device.

3. The time synchronization method according to claim 1, wherein, said step C further comprises the following steps of:

C1, constructing the master clock synchronization domain and each slave clock synchronization domain into an annular synchronization network, and each slave clock synchronization domain registering at the master clock synchronization domain;

C2, the master clock synchronization domain sending the synchronization deviation detection message, the synchronization deviation detection message flowing through each clock synchronization domain in a sequence of registering of each clock synchronization domain and then returning to the master clock synchronization domain, and each slave clock synchronization domain returning a relative time deviation thereof to the synchronization deviation detection message, wherein the relative time deviation refers to a time deviation of each slave clock synchronization domain relative to a last slave clock synchronization domain in a flow direction of the synchronization deviation detection message;

C3, the master clock synchronization domain calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain according to the returned synchronization deviation detection message.

4. The time synchronization method according to claim 1, wherein in said step C, the master clock synchronization domain sends the synchronization deviation detection message to each slave clock synchronization domain in a periodical manner.

5. The time synchronization method according to claim 1, wherein the adjusting step in said step D further comprises:

weighted averaging an absolute value of the time adjustment quantity of each slave clock synchronization domain for a number of times in a predetermined range;

determining a priority level of each slave clock synchronization domain according to a result of the weighted averaging; and

allowing each slave clock synchronization device to adjust among each slave clock synchronization domain according to time accuracy of a core application, adjusting a slave clock synchronization device having a high requirement on time accuracy to a slave clock synchronization domain with a high priority level, and adjusting a slave clock synchronization device having a low requirement on time accuracy to a slave clock synchronization domain with a low priority level.

6. The time synchronization method according to claim 5, further comprising the following steps of:

if any core is newly added, adding the newly added core to a clock synchronization domain with a corresponding priority level, and if a number of newly added cores is greater than a device accommodating threshold of a time clock synchronization domain with a corresponding priority level, then splitting the clock synchronization domain.

7. The time synchronization method according to claim 1, wherein the load of a core is calculated as follows:

determining core load calculation associated factors, said core load calculation associated factors comprising current occupancy rate of the core, core load history, type of an articulated interrupt device of the core, a number of articulated interrupt sources of the core and type of application of the core; and

selecting at least one of the core load calculation associated factors for weighted operation, and using a result of the weighted operation as the load of the core.

8. The time synchronization method according to claim 1, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

11. The time synchronization method according to claim 2, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

12. The time synchronization method according to claim 3, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

13. The time synchronization method according to claim 4, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

14. The time synchronization method according to claim 5, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

15. The time synchronization method according to claim 6, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

16. The time synchronization method according to claim 7, further comprising system clock tick monitoring processing:

the master time synchronization device of the master time synchronization domain at least sampling system ticks twice during each system tick interval, and accumulating sampling values of system ticks;

judging whether system ticks are lost according to a predetermined principle, and if yes, modifying a current system tick value.

9. A time synchronization system for a multi-core system, comprising at least one clock synchronization domain, wherein the time synchronization system is configured as follows:

each core in the multi-core system being allocated respectively to each clock synchronization domain, a core with a lowest load in each clock synchronization domain being selected as a master clock synchronization device in the clock synchronization domain, and other cores being selected as slave clock synchronization devices in the clock synchronization domain;

the clock synchronization domain having the master clock synchronization device with a lowest load among various master clock synchronization devices being selected as a master clock synchronization domain, while other clock synchronization domains being selected as slave clock synchronization domains;

the master clock synchronization domain sending a synchronization deviation detection message to each slave clock synchronization domain, and calculating a time deviation value between each slave clock synchronization domain and the master clock synchronization domain, and when the time deviation value is greater than a permitted deviation value, the master clock synchronization domain calculating a time adjustment quantity of each slave clock synchronization domain and releasing the time adjustment value to each slave clock synchronization domain.

10. The time synchronization system according to claim 9, wherein, the master clock synchronization domain is exteriorly connected with an exterior synchronization source.