METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION

• US 20110185322A1
• Filed: 01/25/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Wong, William S., Limb, Scott Jong Ho, Street, Robert A., Young, Michael Yu Tak
• Granted Patent: US 9,035,673 B2
• Time in Patent Office: Days
• US Class Current: 716/50
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G11C 2029/0403 during or with feedback to manufacture
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.

Claims

1. A method for in-process yield evaluation in an array type of device, comprising:

measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and

analyzing the measured electrical property to identify at least one of the following;

GATE line open defects,

GATE line bridge defects,

DATA line open defects,

DATA line bridge defects, and

interlayer shunt defects.

2. The method of claim 1, wherein the electrical property is electrical resistance.

3. The method of claim 1, wherein the electrical property is electrical capacitance.

4. The method of claim 2,

wherein GATE line open defects are identified through a process including:

measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and

analyzing the measured electrical resistance data to identify GATE line open defects;

wherein the GATE line bridge defects are identified through a process including;

measuring electrical resistance between individual GATE lines, and

analyzing the measured electrical resistance data to identify GATE line bridge defects;

wherein DATA line open defects are identified through a process including;

measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and

analyzing the measured electrical resistance data to identify DATA line open defects;

wherein the DATA line bridge defects are identified through a process including;

measuring electrical resistance between individual DATA lines, and

analyzing the measured electrical resistance data to identify DATA line bridge defects; and

wherein interlayer shunt defects are identified through a process including;

measuring electrical resistance between individual DATA lines and the GATE bus I/O pad, and

analyzing the measured electrical resistance data to identify interlayer shunt defects.

5. The method of claim 4, wherein at least one of the following is performed:

electrical resistance is measured between every individual GATE line and the GATE bus I/O pad;

electrical resistance is measured between every combination of GATE lines;

electrical resistance is measured between every individual DATA line and the DATA bus I/O pad;

electrical resistance is measured between every combination of DATA lines; and

electrical resistance is measured between every individual DATA line and the GATE I/O pad.

6. The method of claim 4, wherein the analyzing the measured electrical resistance data to identify GATE line open defects comprises:

creating a data plot with the measured electrical resistance data with respect to the GATE line number measured;

identifying any irregular data spikes as an open line defect at a corresponding GATE line.

7. The method of claim 4, wherein the analyzing the measured electrical resistance data to identify GATE line bridge defects comprises:

creating a data plot with the measured electrical resistance data with respect to the GATE line number measured;

identifying any irregular data spikes as a bridge line defect at a corresponding GATE line.

8. The method of claim 4, wherein the analyzing the measured electrical resistance data to identify DATA line open defects comprises:

creating a data plot with the measured electrical resistance data with respect to the DATA line number measured;

identifying any irregular data spikes as an open line defect at a corresponding DATA line.

9. The method of claim 4, wherein the analyzing the measured electrical resistance data to identify DATA line bridge defects comprises:

creating a data plot with the measured electrical resistance data with respect to the DATA line number measured;

identifying any irregular data spikes as a bridge line defect at a corresponding DATA line.

10. The method of claim 4, wherein the analyzing the measured electrical resistance data to identify interlayer shunt defects comprises:

creating a data plot with the measured electrical resistance data with respect to the DATA line number measured;

identifying any local minima as a shunt defect at a corresponding DATA line.

11. The method of claim 2, wherein the identified defect type, location, and process state is sent to a defect correction device.

12. The method of claim 2, wherein the defects are identified on one of:

printed organic electronics,

printed circuit boards,

active matrix displays,

passive matrix displays, and

memory arrays.

13. The method of claim 2, wherein analysis of the measured electrical resistance data uses a differential data analysis technique.

14. The method of claim 2, wherein the electrical resistance is measured by a switching matrix which is capable of switching the tension of a testing instrument to each one of the lines, one at a time.

21. The method of claim 2, further comprising:

receiving identified defect types, defect locations, and process state; and

dynamically reconfiguring a die or chip design to account for defects on the substrate based at least partially on the received defect types, defect locations, and process state.

15. A method for in-process correction of defects in an array type of substrate, comprising:

receiving identified defect types, locations, and process state;

dynamically reconfiguring a die or chip design to account for defects on the substrate based at least partially on the received defect types, locations, and process state.

16. The method of claim 15, further comprising:

downloading the reconfigured die or chip design onto a digital lithography system for the printing of a subsequent mask layer for the defective substrate.

17. The method of claim 15, wherein the reconfigured design includes at least one of the following:

a mushroom metal layer, and

a VIA layer.

18. The method of claim 15, further comprising:

correcting line bridge and interlayer shunt defects with laser ablation.

20. The method of claim 17, wherein the reconfigured design utilizes localized line bridging.

19. The method of claim 19, further comprising:

correcting any open line defects created by the correction of line bridge and interlayer shunt defects with laser ablation with at least one of the following;

a mushroom metal layer, and

a VIA layer.

22. A system for in-process yield evaluation for an array type of device, comprising:

a system controller; and

an electrical measurement device, operatively connected to the system controller;

wherein the electrical measurement device measures an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad on the array type of device; and

wherein the system controller analyzes the measured electrical property to identify at least one of the following on the array type of device;

GATE line open defects,

GATE line bridge defects,

DATA line open defects,

DATA line bridge defects, and

interlayer shunt defects.

23. The system of claim 22, wherein the electrical property is electrical resistance.

24. The system of claim 22, wherein the electrical property is electrical capacitance.

25. The system of claim 23, wherein the system controller, operatively connected to the electrical measurement device, detects GATE line open defects through a process including:

measuring electrical resistance between individual GATE lines and a GATE bus I/O pad, and

analyzing the measured electrical resistance data to identify GATE line open defects;

wherein the GATE line bridge defects are identified through a process including;

measuring electrical resistance between individual GATE lines, and

analyzing the measured electrical resistance data to identify GATE line bridge defects;

wherein DATA line open defects are identified through a process including;

measuring electrical resistance between individual DATA lines and the DATA bus I/O pad, and

analyzing the measured electrical resistance data to identify DATA line open defects;

wherein the DATA line bridge defects are identified through a process including;

measuring electrical resistance between individual DATA lines, and

analyzing the measured electrical resistance data to identify DATA line bridge defects; and

wherein interlayer shunt defects are identified through a process including;

measuring electrical resistance between individual DATA lines and the GATE bus I/O pad, and

analyzing the measured electrical resistance data to identify interlayer shunt defects.

26. A system for in-process correction of defects in an array type of substrate, comprising:

a system controller;

a mushroom metal and VIA layer definition module; and

a digital lithography printer;

wherein the mushroom metal and via layer definition module receives defect data from the system controller, where the defect data comprises;

identified defect types,

defect locations, and

a process state; and

wherein the mushroom metal and via layer definition module dynamically reconfigures a die or chip design to account for defects on the substrate based at least partially on the received defect types, locations, and process state.

27. The system of claim 26, further comprising a laser ablation tool operational to correct shunt defects identified by the system controller.

28. The system of claim 26, further comprising:

downloading the reconfigured die or chip design onto a digital lithography system for the printing of a subsequent mask layer for the defective substrate.