High Performance, High Bandgap, Lattice-Mismatched, GaInP Solar Cells

• US 20110186115A1
• Filed: 01/29/2009
• Published: 08/04/2011
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: Alliance For Sustainable Energy LLC
• Original Assignee: Alliance For Sustainable Energy LLC
• Inventors: Carapella, Jeffrey J, Wanlass, Mark W., Steiner, Myles A.
• Granted Patent: US 8,772,628 B2
• Time in Patent Office: Days
• US Class Current: 136/255
• CPC Class Codes: H01L 31/02168 the coatings being antireflective or having enhancing optical properties for the solar cells
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/032 including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
• CPC Class Codes: H01L 31/065 the potential barriers being only of the graded gap type
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/06875 inverted grown metamorphic [IMM] multiple junction solar cells, e.g. III-V compounds inverted metamorphic multi-junction cells
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/1844 comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

High performance, high bandgap, lattice-mismatched, photovoltaic cells (10), both transparent and non-transparent to sub-bandgap light, are provided as devices for use alone or in combination with other cells in split spectrum apparatus or other applications.

Claims

1. A photovoltaic converter, comprising:

a photovoltaic cell comprising GaInP with a bandgap greater than about 1.9 eV and doped to have a homojunction grown lattice-mismatched on a GaAs parent substrate; and

means positioned between the parent substrate and the photovoltaic cell for providing a crystalline epitaxial growth plane on the parent substrate with a lattice constant that matches a relaxed lattice constant of the GaInP photovoltaic cell.

2. The photovoltaic converter of claim 1, wherein the parent substrate is GaAs.

3. The photovoltaic converter of claim 2, wherein said means for providing a crystalline epitaxial growth plane includes a graded layer comprising GaAs_1-xP_x, wherein “

x”

increases until the proportions of As and P in the GaAsP are such that the GaAsP has a lattice constant in the growth plane that matches the relaxed lattice constant of the GaInP photovoltaic cell.

4. The photovoltaic converter of claim 3, wherein “

x”

increases in discrete incremental steps.

5. The photovoltaic converter of claim 4, wherein the graded GaAs_1-xP_x comprises about 6 to 10 steps of GaAs_1-xP_x, each step being about 1.0 to 2.2 μ

m thick, with the phosphorus content increased, and the As content correspondingly decreased, by approximately 4 to 6 percent per step, and with the last step being approximately 30 to 44 percent phosphorus.

6. The photovoltaic converter of claim 5, wherein the GaInP cell includes a base on the back side of the junction adjacent the graded GaAs_1-xP_x and an emitter on the front side of the junction, and wherein the photovoltaic converter further includes:

(i) a double heterostructure comprising a back surface confinement layer between the graded GaAs_1-xP_x and the base and a passivation/window layer on the emitter;

(ii) an electrically conductive grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current;

(iii) an anti-reflection coating on the passivation/window layer between the grid contacts; and

(iv) an electrically conductive back contact on the back side of the parent substrate.

7. The photovoltaic converter of claim 2, wherein the photovoltaic converter has a front side and a back side, the cell is ultra-thin with an emitter on the front side of the junction and a base on the back side of the junction, and wherein the photovoltaic converter further includes:

(i) a double heterostructure comprising a back surface confinement layer between the graded GaAs_1-xP_x and the base and a passivation/window layer on the emitter;

(ii) a front electrically conductive grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current;

(iii) a front anti-reflection coating on the passivation/window layer between the front grid contacts;

(iv) a back electrically conductive grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current; and

(v) a back anti-reflection coating on the back side confinement layer between the front grid contacts.

8. The photovoltaic converter of claim 7, including a transparent handle mounted on the back of the photovoltaic converter.

9. The photovoltaic converter of claim 7, including a transparent handle mounted on the front of the photovoltaic converter.

10. The photovoltaic converter of claim 1, wherein the parent substrate is Ge.

11. The photovoltaic converter of claim 1, wherein the parent substrate is GaP.

12. The photovoltaic converter of claim 1, wherein the parent substrate is Si.

13. The photovoltaic converter of claim 1, wherein the parent substrate is SiGe, or other virtual substrate comprising a commercially available substrate with a compositionally graded layer grown thereon.

14. A photovoltaic converter, comprising:

a photovoltaic cell comprising GaInP with a bandgap greater than 1.9 eV and doped to have a homojunction grown lattice-mismatched on a GaAs parent substrate; and

a graded layer comprising GaAs_1-xP_x, wherein “

x”

increases until the proportions of As and P in the GaAsP are such that the GaAsP has a lattice constant in the growth plane that matches the relaxed lattice constant of the GaInP photovoltaic cell.

15. The photovoltaic converter of claim 14, wherein “

x”

increases in discrete incremental steps.

16. The photovoltaic converter of claim 15, wherein the graded GaAs_1-xP_x comprises 6 to 10 steps of GaAs_1-xP_x each step being about 1.0 to 2.2 μ

m thick, with the phosphorus content increased, and the As content correspondingly decreased, by approximately 4 to 6 percent per step, and with the last step being approximately 30 to 44 percent phosphorus.

17. The photovoltaic converter of claim 16, wherein the GaInP cell includes a base on the back side of the junction adjacent the graded GaAs_1-xP_x and an emitter on the front side of the junction, and wherein the photovoltaic converter further includes:

(i) a double heterostructure comprising a back surface confinement layer between the graded GaAs_1-xP_x and the base and a passivation/window layer on the emitter;

(ii) an electrically conductive grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current;

(iii) an anti-reflection coating on the passivation/window layer between the grid contacts; and

(iv) an electrically conductive back contact on the back side of the parent substrate.

18. The photovoltaic converter of claim 14, wherein the photovoltaic converter has a front side and a back side, the cell is ultra-thin with an emitter on the front side of the junction and a base on the back side of the junction, and wherein the photovoltaic converter further includes:

(i) a double hetero heterostructure comprising a back surface confinement layer between the graded GaAs_1-xP_x and the base and a passivation/window layer on the emitter;

(ii) a front electrically conductive, grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current;

(iii) a front anti-reflection coating on the passivation/window layer between the front grid contacts;

(iv) a back electrically conductive grid on the passivation/window layer comprising doped GaAsP between a metal contact and the passivation/window layer for conducting electric current; and

(v) a back anti-reflection coating on the back side confinement layer between the front grid contacts.

19. The photovoltaic converter of claim 18, including a transparent handle mounted on the back of the photovoltaic converter.

20. The photovoltaic converter of claim 18, including a transparent handle mounted on the front of the photovoltaic converter.

21. The photovoltaic converter of claim 14, wherein the GaInP cell has a n-type emitter in a range of about 500-3000 Å

thick and a p-type base in a range of about 2-4 μ

m thick.

22. A method of fabricating a high bandgap GaInP photovoltaic converter, comprising:

providing a crystalline growth plane that has a lattice constant which matches a relaxed lattice constant of GaInP that has a bandgap between about 1.9 eV and 2.2 eV;

growing a doped GaAsP front contact layer on the crystalline growth plane;

growing a GaInP photovoltaic cell on the doped GaAsP front contact layer; and

growing a doped GaAsP back contact layer on the crystalline growth plane.

23. The method of claim 22, including doping the GaAsP front contact layer is a n-type dopant for an emitter in the GaInP cell, growing an initial thickness of the GaInP cell with no dopant, and growing the remainder of the GaInP cell with a p-type dopant to form a base portion of the GaInP cell while allowing the n-type dopant diffuse from the GaAsP front contact layer into the undoped thickness of the GaInP cell to form an emitter portion of the GaInP cell.

24. The method of claim 23, including growing the GaInP cell in a process that involves an elevated temperature sufficiently high to induce the diffusion of the dopant from the GaAsP front contact layer into the GaInP cell.

25. The method of claim 24, wherein the elevated temperature is in a range of about 600-750°

C.

26. The method of claim 23, including doping only a portion of the GaAsP front contact layer with the n-type dopant for the GaInP, said portion of the GaAsP being a spaced distance away from the GaInP.

27. The method of claim 22, including providing the crystalline growth plane that has a lattice constant which matches a relaxed lattice constant of GaInP that has a bandgap between about 1.9 eV and 2.2 eV by growing a graded layer of GaAs_1-xP_x on a crystalline parent substrate by starting the GaAs_1-xP_x the graded layer with a value of “

x”

that proportions the As and P in the GaAs_1-xP_x in a manner that provides the GaAs_1-xP_x with a lattice constant that matches the lattice constant of the parent substrate and ends with a value of “

x”

that proportions the Ga and P in the GaAs_1-xP_x in a manner that provides the GaAs_1-xP_x with a growth plane lattice constant that matches a relaxed lattice constant of GaInP with a target bandgap between about 1.9 eV and 2.2 eV.

28. The method of claim 27, wherein the parent substrate is GaAs.

29. The method of claim 28, wherein the graded GaAs_1-xP_x comprises 6 to 10 steps of GaAs_1-xP_x each step being about 1.0 to 2.2 μ

m thick, with the phosphorus content increased, and the As content correspondingly decreased, by approximately 4 to 6 percent per step, and with the last step being approximately 30 to 44 percent phosphorus.

30. The method of claim 27, including growing a front passivation/window layer between the doped GaAsP front contact layer and the emitter of the GaInP cell and growing a back side confinement layer between the base of the GaInP cell and the doped GaAsP back contact layer.

31. The method of claim 30, including affixing a metal front contact grid on the doped GaAsP front contact layer, removing the doped GaAsP front contact layer between the front grids, applying a front anti-reflection coating on the passivation/window layer, mounting the front of the cell on a transparent handle, removing the parent substrate and the graded layer, affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer between the back grids, and applying a back anti-reflection coating on the back surface confinement layer.

32. The method of claim 31, including growing an etch-stop layer between graded layer and the GaAsP back contact layer, removing the substrate and graded layer by etching them away with an etchant that is selective for the substrate and graded layer and does not react with the etch-stop layer, and then removing the etch-stop layer.

33. The method of claim 32, including growing the cell upright.

34. The method of claim 32, including growing the cell inverted.

35. The method of claim 30, including affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer between the grids, applying a back anti-reflection coating on the back surface confinement layer, mounting the back of the cell on a transparent handle, and removing the parent substrate and graded layer.

36. The method of claim 35, including growing an etch-stop layer between graded layer and the GaAsP front contact layer, removing the substrate and graded layer by etching them away with an etchant that is selective for the substrate and graded layer and does not react with the etch-stop layer, and then removing the etch-stop layer.

37. The method of claim 36, including growing the cell upright.

39. The method of claim 30, including affixing a metal front contact grid on the doped GaAsP front contact layer, removing the doped GaAsP front contact layer between the front grids, applying a front anti-reflection coating on the passivation/window layer, mounting the front of the cell on an interim handle, removing the parent substrate and the graded layer, affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer between the back grids, applying a back anti-reflection coating on the back surface confinement layer, mounting the back of the cell on a permanent transparent handle, and removing the interim handle.

38. The method of claim 367, including growing the cell inverted.