Touch Panel Sensing Circuit

• US 20110186359A1
• Filed: 04/07/2010
• Published: 08/04/2011
• Est. Priority Date: 02/04/2010
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Liu, Chia-Lin, Mo, Chi-Neng, Chen, Chih-Chung, Chen, Yi-Chun, Chen, Ke-Horng, Li, Huai-An, Chen, Chi-Lin
• Granted Patent: US 8,259,087 B2
• Time in Patent Office: Days
• US Class Current: 178/18.06
• CPC Class Codes: G06F 3/04182 Filtering of noise external to the device and not generated by digitiser components
• CPC Class Codes: G06F 3/044 by capacitive means

Abstract

In a capacitance sensing analog circuit of a touch panel sensing circuit, by raising a magnitude of a current flowing through a sensing capacitor to form an amplified sensing capacitance, while sensing the amplified sensing capacitance with the aid of pulse width modulation signals, higher resolution of the original sensing capacitance may thus be achieved. Besides, by using a self-calibrating capacitance sensing circuit on the touch panel sensing circuit, linear errors and DC errors of an output signal of the capacitance sensing analog circuit may be filtered off, and thereby resolution of a capacitance amplifying ratio may be effectively raised so as to relieve errors within the capacitance amplifying ratio caused by noises.

Claims

1. A touch panel sensing circuit, comprising:

a capacitance sensing analog circuit, comprising;

a first current mirror, comprising;

a first transistor, having a source coupled to a DC voltage source, and having a drain coupled to a gate of the first transistor and a sensing capacitor of a touch panel; and

a second transistor, having a gate coupled to the gate of the first transistor, and having a source coupled to the source of the first transistor;

a second current mirror, comprising;

a third transistor, having a drain coupled to a drain of the second transistor, and having a gate coupled to the DC voltage source;

a fourth transistor, having a gate coupled to the gate of the third transistor, and having a drain coupled to the drain of the third transistor; and

an operational amplifier, having an input terminal coupled to the source of the third transistor, and having an output terminal coupled to the source of the fourth transistor;

a switch module, coupled to the drain of the fourth transistor, and generating an output signal according to a voltage level at the drain of the fourth transistor; and

an equivalent capacitor, having a first terminal coupled to the source of the third transistor, and having a second terminal coupled to a ground;

a capacitance sensing digital circuit, for generating a cycle accumulating signal according to a duty cycle of the output signal; and

a digital signal processing unit, for linearizing the cycle accumulating signal so as to generate a linearized signal, and thereby for determining a capacitance of the sensing capacitor;

wherein a width-to-length ratio of the fourth transistor is an at-least one multiple of a width-to-length ratio of the third transistor.

2. The touch panel sensing circuit of claim 1,

wherein the capacitance sensing analog circuit further comprises:

a first switch transistor, having a drain coupled to the drain of the first transistor;

a first comparator, having a positive input terminal coupled to a reference voltage, having a negative input terminal coupled to the source of the first switch transistor, and having an output terminal coupled to the gate of the first switch transistor;

a second switch transistor, having a drain coupled to the source of the first switch transistor, having a gate coupled to a first clock signal, and having a source coupled to a first terminal of the sensing capacitor; and

a third switch transistor, having a gate coupled to a second clock signal, having a drain coupled to the source of the second switch transistor, and having a source coupled to a second terminal of the sensing capacitor and to the ground;

wherein a phase of the first clock signal is reverse to a phase of the second clock signal.

3. The touch panel sensing circuit of claim 1,

wherein the switch module comprises:

a second comparator, having a positive input terminal coupled to the drain of the fourth transistor, and having a negative input terminal coupled to a first reference voltage;

a third comparator, having a positive input terminal coupled to a second reference voltage, and having a negative input terminal coupled to the positive input terminal of the second comparator; and

a D flip-flop, having a set terminal coupled to an output terminal of the second comparator, and having a reset terminal coupled to an output terminal of the third comparator;

wherein the capacitance sensing analog circuit further comprises;

a fourth switch transistor, having a gate coupled to a positive output terminal of the D flip-flop, and having a source coupled to the ground; and

a resistor, having a first terminal coupled to the drain of the fourth transistor, and having a second terminal coupled to the drain of the fourth switch transistor.

4. The touch panel sensing circuit of claim 1,

wherein capacitance sensing digital circuit comprises:

a controlling circuit, comprising;

a first counter, for counting a sensing cycle of the capacitance sensing digital circuit;

a second counter, for counting a processing cycle of the capacitance sensing digital circuit; and

a timing controlling unit, for initiating the sensing cycle or the processing cycle of the capacitance sensing digital circuit according to counts of the first and second counters and to a clock signal of the capacitance sensing analog circuit, wherein both the first and second counters count the sensing cycle and the processing cycle according to the clock signal;

a pulse-width-to-digital converting module, comprising;

a first logic gate, having a first input terminal coupled to the timing controlling unit so as to initiate the sensing cycle, and having a second input terminal coupled to the output signal;

an accumulating unit, having a first input terminal coupled to an output terminal of the first logic gate logic gate, and having a second input terminal coupled to the clock signal; and

a second logic gate, having a first input terminal coupled to a first output terminal of the accumulating unit so as to receive the cycle accumulating signal, and having a second input terminal coupled to the timing controlling unit so as to initiate the processing cycle.

5. A touch panel sensing circuit, comprising:

a capacitance sensing analog circuit, comprising;

a first current mirror, comprising;

a first transistor, having a source coupled to a DC voltage source, and having a drain coupled to a gate of the first transistor and to a sensing capacitor of a touch panel;

a second transistor, having a gate coupled to the gate of the first transistor, and having a source coupled to the source of the first transistor; and

a third transistor, having a gate coupled to the gate of the first transistor, and having a source coupled to the source of the first transistor;

a second current mirror, comprising;

a fourth transistor, having a drain coupled to a drain of the second transistor, and having a gate coupled to the DC voltage source;

a transistor set, comprising a plurality of transistors connected in parallel, and drains of the plurality of transistors comprised by the transistor set being coupled to the drain of the fourth transistor; and

a first operational amplifier, having an input terminal coupled to a source of the fourth transistor, and having an output terminal coupled to sources of the plurality of transistors comprised by the transistor set;

a third current mirror, comprising;

a fifth transistor, having a drain coupled to a drain of the third transistor, and having a gate coupled to the DC voltage source;

a sixth transistor, having a drain coupled to the drain of the fifth transistor, and having a gate coupled to the gate of the fifth transistor; and

a second operational amplifier, having an input terminal coupled to a source of the fifth transistor, and having an output terminal coupled to a source of the sixth transistor;

a first switch module, coupled to the drain of the fourth transistor, the first switch module being used for generating a second output signal according to a voltage level at the drain of the fourth transistor;

a first equivalent capacitor, having a first terminal coupled to the source of the fifth transistor, and having a second terminal coupled to a ground;

a second equivalent capacitor, having a first terminal coupled to the source of the fourth transistor, and having a second terminal coupled to the ground; and

a calibration unit, coupled to gates of the plurality of transistors comprised by the transistor set, the calibration unit being used for generating a third output signal and a capacitance amplifying ratio adjusting signal according to a duty cycle ratio between the first output signal and the second output signal, and being used for transmitting the capacitance amplifying ratio adjusting signal to the plurality of transistors comprised by the transistor set so as to control a width-to-length ratio of the transistor set;

a capacitance sensing digital circuit, for generating a cycle accumulating signal according to a duty cycle of the third output signal; and

a digital signal processing unit, for linearizing the cycle accumulating signal so as to generate a linearized signal, for determining a capacitance of the sensing capacitor;

wherein a width-to-length ratio between the transistor set and the fourth transistor is higher than a width-to-length ratio between the sixth transistor and the fifth transistor.

6. The touch panel sensing circuit of claim 5,

wherein the capacitance sensing analog circuit further comprises:

a first switch transistor, having a drain coupled to the drain of the first transistor;

a first comparator, having a positive input terminal coupled to a reference voltage, having a negative input terminal coupled to the source of the first switch transistor, and having an output terminal coupled to the gate of the first switch transistor;

a second switch transistor, having a drain coupled to the source of the first switch transistor, having a gate coupled to a first clock signal, and having a source coupled to a first terminal of the sensing capacitor; and

a third switch transistor, having a gate coupled to a second clock signal, having a drain coupled to the source of the second switch transistor, and having a source coupled to a second terminal of the sensing capacitor and to the ground;

wherein phases of the first clock signal and the second clock signal are reverse to each other.

7. The touch panel sensing circuit of claim 5,

wherein the first switch module comprises:

a second comparator, having a positive input terminal coupled to the drain of the fifth transistor, and having a negative input terminal coupled to a first reference voltage;

a third comparator, having a positive input terminal coupled to a second reference voltage, and having a negative input terminal coupled to the positive input terminal of the second comparator; and

a first D flip-flop, having a set terminal coupled to an output terminal of the second comparator, having a reset terminal coupled to an output terminal of the third comparator, and having an negative output terminal coupled to the calibration unit so as to output the first output signal;

wherein the second switch module comprises;

a fourth comparator, having a positive input terminal coupled to the drain of the fourth transistor, and having a negative input terminal coupled to the first reference voltage;

a fifth comparator, having a positive input terminal coupled to the second reference voltage, and having a negative input terminal coupled to the positive input terminal of the fourth comparator; and

a second D flip-flop, having a set terminal coupled to an output terminal of the fourth comparator, having a reset terminal coupled to an output terminal of the fifth comparator, and having a negative output terminal coupled to the calibration unit so as to output the second output signal;

wherein the capacitance sensing analog circuit further comprises;

a fourth switch transistor, having a gate coupled to a positive output terminal of the first D flip-flop, and having a source coupled to the ground;

a first resistor, having a first terminal coupled to the drain of the fifth transistor, and having a second terminal coupled to the drain of the fourth switch transistor;

a fifth switch transistor, having a gate coupled to a positive output terminal of the second D flip-flop, and having a source coupled to the ground; and

a second resistor, having a first terminal coupled to the drain of the fourth transistor, and having a second terminal coupled to the drain of the fifth switch transistor.

8. The touch panel sensing circuit of claim 5,

wherein the capacitance sensing digital circuit comprises:

a controlling circuit, comprising;

a first counter, for counting a sensing cycle of the capacitance sensing digital circuit;

a second counter, for counting a processing cycle of the capacitance sensing digital circuit; and

a timing controlling unit, for initiating the sensing cycle or the processing cycle of the capacitance sensing digital circuit according to counts of the first and second counters and a clock signal of the capacitance sensing analog circuit, wherein the first and second counters count the sensing cycle and the processing cycle according to the clock signal, and the timing controlling unit issues an initialized calibration signal to the capacitance sensing analog circuit at the processing cycle;

a pulse-width-to-digital transforming module, comprising;

a first logic gate, having a first input terminal coupled to the timing controlling unit so as to initiate the sensing cycle, and having a second input terminal coupled to the third output signal;

an accumulating unit, having a first input terminal coupled to an output terminal of the first logic gate, having a second input terminal coupled to the clock signal, and having a first output terminal for issuing a capacitance amplifying ratio adjusting parameter to the capacitance sensing analog circuit; and

a second logic gate, having a first input terminal coupled to a second output terminal of the accumulating unit so as to receive the cycle accumulating signal, and having a second input terminal coupled to the timing controlling unit so as to initiate the processing cycle;

wherein the calibration unit controls a width-to-length ratio according to the capacitance amplifying ratio adjusting parameter.