CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER
First Claim
1. A semiconductor wafer configured for wafer level testing, comprising:
- a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;
separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;
a conductive grid interconnecting a group of said electronic devices and having an external portion external to the devices of said group and an internal portion internal to the devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the devices of said group;
interconnection pads positioned on the devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group.
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Accused Products
Abstract
A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.
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Citations
21 Claims
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1. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges; separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other; a conductive grid interconnecting a group of said electronic devices and having an external portion external to the devices of said group and an internal portion internal to the devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the devices of said group; interconnection pads positioned on the devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method comprising:
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forming scribe lines on a semiconductor wafer; forming a plurality of electronic devices integrated on said semiconductor wafer and separated from each other by said scribe lines; forming a respective plurality of interconnection pads on each electronic device respectively; forming a conductive grid on said semiconductor wafer, said forming said conductive grid including; forming an external portion of said conductive grid along said scribe lines; forming an internal portion of said conductive grid within said electronic devices; and connecting one of the interconnection pads of each electronic device to one of the interconnection pads of adjacent one of the electronic devices and to said conductive grid, forming power supply lines common to said electronic devices. - View Dependent Claims (16, 17, 18)
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19. A semiconductor wafer configured for wafer level testing, comprising:
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a plurality of electronic devices integrated on the semiconductor wafer, each electronic device including a power supply pad; scribe line areas separating the electronic devices from each other; a conductive grid of conductive lines extending lengthwise in the scribe line areas, wherein the grid of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines; and a plurality of bridging connectors electrically connecting the conductive grid to the power supply pad of each of the electronic devices. - View Dependent Claims (20, 21)
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Specification