CIRCUIT ARCHITECTURE FOR THE PARALLEL SUPPLYING DURING AN ELECTRIC OR ELECTROMAGNETIC TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER

• US 20110186838A1
• Filed: 02/07/2011
• Published: 08/04/2011
• Est. Priority Date: 08/07/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto
• Granted Patent: US 8,378,346 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A circuit architecture provides for the parallel supplying of power during electric or electromagnetic testing of electronic devices integrated on a same semiconductor wafer and bounded by scribe lines. The circuit architecture comprises a conductive grid interconnecting the electronic devices and having a portion external to the devices and a portion internal to the devices. The external portion extends along the scribe lines; and the internal portion extends within at least a part of the devices. The circuit architecture includes interconnection pads between the external portion and the internal portion of the conductive grid and provided on at least a part of the devices, the interconnection pads forming, along with the internal and external portions, power supply lines which are common to different electronic devices of the group.

Claims

1. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer wherein said electronic devices have edges;

separation scribe lines bounding the edges of the electronic devices and separating the electronic devices from each other;

a conductive grid interconnecting a group of said electronic devices and having an external portion external to the devices of said group and an internal portion internal to the devices of said group, the external portion of said conductive grid extending along said separation scribe lines, and the internal portion extending within the devices of said group;

interconnection pads positioned on the devices of the group and coupling said external portion and said internal portion of said conductive grid being provided on the devices of said group, said interconnection pads forming, along with said internal and external portions, power supply lines which are common to different electronic devices of said group.

2. The semiconductor wafer according to claim 1, wherein each electronic device of said group comprises a power supply pad at one of the edges of the electronic device, the power supply pad being connected with the external portion of said conductive grid.

3. The semiconductor wafer according to claim 1, wherein each electronic device of said group comprises a plurality of power supply pads at the edges of the electronic device, each power supply pad being connected to the external portion of said conductive grid.

4. The semiconductor wafer according to claim 1, wherein said external portion includes a conductive bridging connection between power supply pads of adjacent electronic devices of the group.

5. The semiconductor wafer according to claim 1, wherein one of the electronic devices of the group includes two interconnection and power supply pads and said internal portion includes an electric connection between the interconnection and power supply pads.

6. The semiconductor wafer according to claim 1, wherein said internal portion includes crossing connections.

7. The semiconductor wafer according to claim 1, further comprising an insulating layer positioned on one of said scribe lines, wherein two adjacent electronic devices of said group include respective interconnection pads and said external portion includes a metal layer positioned on said insulating layer and extending between the respective interconnection pads of the two adjacent electronic devices.

8. The semiconductor wafer according to claim 1, further comprising an insulating layer extending within and at least partially filling one of said scribe lines, wherein said external portion comprises a metal layer positioned on the insulating layer.

9. The semiconductor wafer according to claim 1, wherein said interconnection pads comprise power supply dummy pads and signal dummy pads.

10. The semiconductor wafer according to claim 1, wherein said external portion and said internal portion of said conductive grid are orthogonal to each other.

11. The semiconductor wafer according to claim 1, wherein said external portion includes a grid of conductive lines extending lengthwise in the scribe lines, respectively.

12. The semiconductor wafer according to claim 11, wherein the grid of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines, said first conductive line being insulated from the second conductive lines at crossover points.

13. The semiconductor wafer according to claim 1, further comprising an insulating layer extending within and at least partially filling one of said scribe lines, wherein the external portion includes:

a conductive line buried in said insulating layer;

a bridging connector extending on said insulating layer and on one of the devices, the bridging connector being coupled to one of the interconnection pads positioned on said one of the devices; and

a connection via extending through a portion of the insulating layer and connecting the bridging connector to said buried conductive line.

14. The semiconductor wafer according to claim 1, wherein the external portion includes a fuse link.

15. A method comprising:

forming scribe lines on a semiconductor wafer;

forming a plurality of electronic devices integrated on said semiconductor wafer and separated from each other by said scribe lines;

forming a respective plurality of interconnection pads on each electronic device respectively;

forming a conductive grid on said semiconductor wafer, said forming said conductive grid including;

forming an external portion of said conductive grid along said scribe lines;

forming an internal portion of said conductive grid within said electronic devices; and

connecting one of the interconnection pads of each electronic device to one of the interconnection pads of adjacent one of the electronic devices and to said conductive grid, forming power supply lines common to said electronic devices.

16. The method of claim 15 wherein forming said internal portion comprises electrically connecting two interconnection pads of a same electronic device of the electronic devices.

17. The method of claim 15, comprising supplying a voltage to all of said electronic devices simultaneously through said conductive grid.

18. The method of claim 17, comprising simultaneously testing said electronic devices.

19. A semiconductor wafer configured for wafer level testing, comprising:

a plurality of electronic devices integrated on the semiconductor wafer, each electronic device including a power supply pad;

scribe line areas separating the electronic devices from each other;

a conductive grid of conductive lines extending lengthwise in the scribe line areas, wherein the grid of conductive lines includes first conductive lines extending substantially parallel to each other and second conductive lines extending substantially parallel to each other and substantially orthogonally to the first conductive lines; and

a plurality of bridging connectors electrically connecting the conductive grid to the power supply pad of each of the electronic devices.

20. The semiconductor wafer according to claim 19, wherein the first conductive lines are insulated from the second conductive lines at crossover points at which one of the first conductive lines crosses one of the second conductive lines.

21. The semiconductor wafer according to claim 19, further comprising:

an insulating layer extending within and at least partially filling said scribe lines, wherein the conductive lines are buried in said insulating layer, the bridging connectors extending on said insulating layer and on at least one of the devices, the bridging connector being coupled to one of the interconnection pads positioned on said one of the devices; and

a plurality of connection via extending through a portion of the insulating layer and respectively connecting respective bridging connectors to respective conductive lines.