Method and System for Hermetically Sealing Packages for Optics

• US 20110186839A1
• Filed: 04/13/2011
• Published: 08/04/2011
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Inventors: Yang, Xiao, Chen, Dongmin
• Granted Patent: US 8,288,851 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G02B 26/0833 the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD G02B26/0825 takes precedence; micromechanical devices in general B81B
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: Y10T 156/1092 : All laminae planar and face to face
• CPC Class Codes: Y10T 156/1093 : with covering of discrete laminae with additional lamina

Abstract

A system for hermetically sealing devices includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

Claims

1. A MEMS package adapted for wafer level probing of MEMS devices, the MEMS package comprising:

a substrate comprising;

a plurality of MEMS chips, each of the plurality of MEMS chips including a plurality of devices, the plurality of MEMS chips being arranged in a spatial manner as a first array configuration, the first array configuration including a first separation region extending in a first direction between each of the plurality of individual chips and a second separation region extending in a second direction between each of the plurality of individual chips, the first direction being oriented at an angle with respect to the second direction; and

one or more bond pads located adjacent to each of the plurality of MEMS chips, wherein the one or more bond pads are in electrical communication with the plurality of devices in each of the plurality of MEMS chips; and

a transparent member of a predetermined thickness, the transparent member comprising;

a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array aligned with the first array configuration, and wherein each of the plurality of recessed regions are bordered by a standoff region joined to the substrate, the standoff region having a thickness defined by a portion of the predetermined thickness; and

one or more access regions passing through the transparent member and providing wafer level probing access to the one or more bond pads.

2. The MEMS package of claim 1 wherein an interface between the standoff region and the substrate comprises a hermetic seal.

3. The MEMS package of claim 1 wherein each of the plurality of MEMS chips are hermetically sealed within one of the plurality of recessed regions.

4. The MEMS package of claim 1 wherein the plurality of devices comprises at least one of charge coupled devices, sensing devices, or integrated circuit devices.

5. The MEMS package of claim 1 wherein the plurality of devices comprise deflection devices.

6. The MEMS package of claim 5 wherein the deflection devices comprise micro-mirror structures.

7. The MEMS package of claim 1 wherein the one or more bond pads comprise a first set of bond pads located adjacent to a first side of each of the plurality of MEMS chips.

8. The MEMS package of claim 7 further comprising a second set of bond pads located adjacent to a second side of each of the plurality of MEMS chips, the second side being opposite to the first side.

9. The MEMS package of claim 7 further comprising one or more additional sets of bond pads, each of the one or more additional sets of bond pads being located adjacent an additional side of each of the plurality of MEMS chips, the additional side being oriented 90 degrees with respect to the first side.

10. The MEMS package of claim 1 wherein one or more access regions comprise a plurality of holes passing through the transparent member.

11. The MEMS package of claim 1 wherein the one or more bond pads are located in at least one of the first separation region or the second separation region.

12. The MEMS package of claim 1 wherein the transparent member comprises an antireflective coating disposed overlying surface regions of each of the plurality of recessed regions.

13. The MEMS package of claim 1 wherein the transparent member comprises a first transparent member overlying a second transparent member including the standoff region.

14. The MEMS package of claim 1 wherein the transparent member is characterized by a thickness ranging from about 0.1 mm to 1.2 mm.

15. The MEMS package of claim 1 wherein each of the plurality of MEMS chips is maintained within an inert environment within one of the plurality of recessed regions.

16. The MEMS package of claim 1 wherein the inert environment is selected from nitrogen, argon, or a mixture of nitrogen and argon.

17. The MEMS package of claim 1 wherein each of the plurality of recessed regions comprises a first surface region opposing a second surface region, at least one of the first surface region or the second surface region being characterized by a root mean square surface roughness of less than or equal to 2 Å

for a 2 μ

m by 2 μ

m area.

18. The MEMS package of claim 1 wherein each of the plurality of recess regions has a depth of about 0.5 mm and less.

19. The MEMS package of claim 1 wherein the transparent member comprises a first side and a second side, the first side being parallel to the second side, the first side and the second side being coated with an antireflective material.

20. The MEMS package of claim 1 wherein each of the plurality of recessed regions has a peripheral region that forms an aperture region overlying a portion of one of the plurality of MEMS chips.