Gallium Nitride Power Devices Using Island Topography

• US 20110186858A1
• Filed: 02/03/2011
• Published: 08/04/2011
• Est. Priority Date: 08/04/2009
• Status: Active Grant

• Current Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Original Assignee: GaN Systems Inc. (Infineon Technologies AG)
• Inventors: Roberts, John, Klowak, Greg, Mizan, Ahmad, Patterson, Girvan
• Granted Patent: US 9,029,866 B2
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor. A plurality of connections to the gate electrodes are provided at each interstice defined by corners of the first island electrodes and the second island electrodes.

Claims

1. A semiconductor device comprising:

a substrate;

a semiconductor layer formed on a main surface of the substrate;

a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer, each side of said first island electrodes is opposite a side of said second island electrodes;

a plurality of strip electrodes that are formed in a region between each said first island electrode and each said second island electrode on the semiconductor layer, said strip electrodes for serving as gate electrodes of a multi-island transistor, said first island electrodes for serving as source electrodes, said second island electrodes for serving as drain electrodes;

a plurality of connections to each of said first island electrodes and said second island electrodes; and

a plurality of connections to said gate electrodes at each interstices defined by corners of said first island electrodes and said second island electrodes.

2. The device of claim 1, wherein said plurality of connections to each of said first island electrodes are vias, said plurality of connections to each of said second island electrodes are bumps.

3. The device of claim 1, wherein said island electrodes are each a four-sided figure.

4. The device of claim 1, wherein said island electrodes islands are triangular shaped.

5. The device of claim 1, wherein said island electrodes are a combination of various variants of polygon shapes that allow said alternative arrangement.

6. The device of claim 1, further comprising a low resistance metal strap connecting each gate electrode to a plurality of gate pads.

7. The device of claim 1, further comprising one or more epitaxial layers in between said substrate and said semiconductor layer.

8. The device of claim 7, further comprising a plurality of epitaxial layers and one or more field plates, wherein each said field plate is positioned between successive epitaxial layers.

9. The device of claim 1, wherein the semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.

10. A semiconductor device comprising:

a substrate;

a semiconductor layer formed on a main surface of the substrate;

a plurality of first island electrodes and a plurality of second island electrodes spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer, each side of said first island electrodes is opposite a side of said second island electrodes;

an insulating film formed on the semiconductor layer having a plurality of openings that expose at least one of the first island electrodes, the second island electrodes and common electrode connections areas; and

a plurality of connections formed on the plurality of openings that expose said at least one of the first island electrodes and the second island electrodes.

11. The device according to claim 10, wherein a portion of the plurality of connections are through-substrate via connections and further comprises a large single electrode common pad formed at the base of the multiple through-substrate vias.

12. The device according to claim 10, wherein the islands are predominately rectangular shaped.

13. The device according to claim 10, wherein the islands are predominately triangular shaped.

14. The device according to claim 10, wherein the islands are a combination of various different polygon shapes to optimise active area usage.

15. The device according to claim 10, further comprising

one or more metal layers connecting the plurality of first island electrodes to a common first electrode gold bump connection;

and

another one or more metal layers connecting the plurality of second island electrodes to a common second electrode gold bump connection.

16. The device according to claim 10, wherein the plurality of first island electrodes have a plurality of castellated peninsulas coming out from each of its sides, which are interlaced into a plurality of castellated peninsulas coming out from each of the sides of the plurality of second island electrodes.

17. The device of claim 10, further comprising:

a plurality of third stripe electrodes that are formed in a region between each first island electrode and each second island electrode on the semiconductor layer for serving as gate electrodes of a multi-island transistor, said first island electrodes for serving as source electrodes, said second island electrodes for serving as drain electrodes;

wherein said insulating film further comprises a plurality of openings that expose the third electrodes and wherein said plurality of ball or bump connections are also formed on the plurality of openings that expose the third electrodes.

18. The device according to claim 17 wherein a layer of p-type AlGaN material is deposited under the gate electrode to create an enhancement device.

19. The device according to claim 17 wherein a layer of p-type GaN material is deposited under the gate electrode to create an enhancement device.

20. The device of claim 10 wherein the semiconductor layer is a hetero layer consisting of a layer of undoped gallium nitride beneath a layer of undoped aluminum gallium nitride.