INTEGRATED CIRCUIT

• US 20110186919A1
• Filed: 07/14/2009
• Published: 08/04/2011
• Est. Priority Date: 07/23/2008
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Noort, Wibo D., Zaato, Francis, Letavic, Theodore J.
• Granted Patent: US 9,331,086 B2
• Time in Patent Office: Days
• US Class Current: 257/298
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03M 1/802 using capacitors, e.g. neuron-mos transistors, charge coupled devices
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

Claims

1. Integrated circuit, comprising:

at least one first group each having at least one analog unit;

at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell;

wherein each many-times-programmable cell comprises at least one MOS transistor having a floating gate with a tunnel oxide and a first capacitor coupled to the floating gate;

wherein the capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.

2. Integrated circuit according to claim 1, wherein the first capacitor comprises a tunnel oxide as dielectric material, wherein a tunneling current is induced when a programming voltage across the many-time-programmable cell is sufficiently high and wherein a charge which has tunneled remains trapped when the programming voltage is reduced.

3. Integrated circuit according to claim 1, wherein the integrated circuit is a CMOS implementation and the first capacitor is implemented as a transistor with its gate coupled to the floating gate.

4. Integrated circuit according to claim 1, wherein the integrated circuit is a BiCMOS implementation and the first capacitor is implemented as a capacitor coupled between the floating gate and a base poly layer.

6. Integrated circuit according to claim 1, wherein a thickness of the tunnel oxide is from 50-100 Å

, such as 70 Å

, and the programming voltage is preferably 12V.

7. Electronic device, such as a phased-array antenna, a hybrid, an oscillator, a filter, a matching device, comprising an integrated circuit according to claim 1.

5. Integrated circuit according to wherein the at least one analog unit comprises at least one of a capacitor, an inductor, and a time delay unit.