POWER SEMICONDUCTOR DEVICE

• US 20110186927A1
• Filed: 01/26/2011
• Published: 08/04/2011
• Est. Priority Date: 01/29/2010
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kawano, Takahiro, KAWAGUCHI, Yusuke
• Application Number:
  US13/014,436
• Publication Number:
  US 20110186927A1
• Time in Patent Office: Days
• US Class Current: 257/342
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

According to one embodiment, a power semiconductor device includes a first insulating film and a second insulating film. The first insulating film has a first dielectric constant and is formed on a bottom surface and a side surface of a trench formed by a second semiconductor layer. The trench is in contact with a fourth semiconductor layer and extends from a surface of the fourth semiconductor layer through a third semiconductor layer to the second semiconductor layer. The second insulating film is formed on a side surface of the trench formed by the third semiconductor layer and a side surface of the trench formed by the fourth semiconductor layer, being connected to the first insulating film. The second insulating film has a second dielectric constant higher than the first dielectric constant. The gate electrode is buried in the trench via the first and second insulating films.

Claims

1. A power semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of the first conductivity type formed on a first major surface of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer;

a third semiconductor layer of a second conductivity type selectively formed in a surface of the second semiconductor layer;

a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer;

a first insulating film having a first dielectric constant and formed on a bottom surface and a side surface of a trench formed by the second semiconductor layer, the trench being in contact with the fourth semiconductor layer and extending from a surface of the fourth semiconductor layer through the third semiconductor layer to the second semiconductor layer;

a second insulating film formed on a side surface of the trench formed by the third semiconductor layer and a side surface of the trench formed by the fourth semiconductor layer, the second insulating film being connected to the first insulating film on the side surface of the trench formed by the second semiconductor layer, and the second insulating film having a second dielectric constant higher than the first dielectric constant;

a gate electrode buried in the trench via the first insulating film and the second insulating film;

an interlayer insulating film formed on the gate electrode;

a first main electrode electrically connected to a second major surface of the first semiconductor layer on a side opposite to the first major surface; and

a second main electrode formed on the surface of the fourth semiconductor layer and on the interlayer insulating film, electrically connected to the third semiconductor layer and the fourth semiconductor layer, and insulated from the gate electrode by the interlayer insulating film.

2. The device according to claim 1, wherein the gate electrode oppose the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via the second insulating film.

3. The device according to claim 1, wherein an end of the first insulating film on the second main electrode side is formed on the first main electrode side of a junction interface between the second semiconductor layer and the third semiconductor layer.

4. The device according to claim 1, wherein the first insulating film has a thicker film thickness than the second insulating film.

5. The device according to claim 1, further comprising:

a fifth semiconductor layer of the second conductivity type having a higher impurity concentration than the third semiconductor layer and formed between the second main electrode and the third semiconductor layer.

6. The device according to claim 1, wherein the second insulating film is made of one of SiN, Al₂O₃, and HfO₂.

7. A power semiconductor device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of the first conductivity type formed on a first major surface of the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer;

a third semiconductor layer of a second conductivity type selectively formed in a surface of the second semiconductor layer;

a fourth semiconductor layer of the first conductivity type selectively formed in a surface of the third semiconductor layer;

a first insulating film having a first dielectric constant and formed on a bottom surface and a side surface of a trench formed by the second semiconductor layer, the trench being in contact with the fourth semiconductor layer and extending from a surface of the fourth semiconductor layer through the third semiconductor layer to the second semiconductor layer;

a second insulating film formed on a side surface of the trench formed by the third semiconductor layer and a side surface of the trench formed by the fourth semiconductor layer, the second insulating film being connected to the first insulating film on the side surface of the trench formed by the second semiconductor layer, and the second insulating film having a second dielectric constant higher than the first dielectric constant;

a buried electrode buried in the trench via the first insulating film;

a third insulating film formed above the buried electrode;

a gate electrode insulated from the buried electrode by the third insulating film and buried in the trench via the second insulating film;

an interlayer insulating film formed on the gate electrode;

a first main electrode electrically connected to a second major surface of the first semiconductor layer on a side opposite to the first major surface; and

a second main electrode formed on the surface of the fourth semiconductor layer and on the interlayer insulating film, electrically connected to the third semiconductor layer and the fourth semiconductor layer, and insulated from the gate electrode by the interlayer insulating film.

8. The device according to claim 7, wherein the buried electrode is electrically connected to the second main electrode.

9. The device according to claim 7, wherein the third insulating film is made of a same material as the first insulating film and joined with the first insulating film.

10. The device according to claim 7, wherein the third insulating film is made of a same material as the second insulating film and joined with the second insulating film.

11. The device according to claim 7, wherein the third insulating film includes:

a portion joined with the first insulating film and made of a same material as the first insulating film; and

one other portion joined with the second insulating film and made of a same material as the second insulating film.

12. The device according to claim 7, wherein the gate electrode oppose the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer via the second insulating film.

13. The device according to claim 7, wherein an end of the first insulating film on the second main electrode side is formed on the first main electrode side of a junction interface between the second semiconductor layer and the third semiconductor layer.

14. The device according to claim 7, wherein the first insulating film has a thicker film thickness than the second insulating film.

15. The device according to claim 7, further comprising:

a fifth semiconductor layer of the second conductivity type having a higher impurity concentration than the third semiconductor layer and formed between the second main electrode and the third semiconductor layer.

16. The device according to claim 7, wherein an end of the buried electrode on the second main electrode side is formed on the first main electrode side of a junction interface between the second semiconductor layer and the third semiconductor layer.

17. The device according to claim 7, wherein an end of the third insulating film on the second main electrode side is formed on the first main electrode side of a junction interface between the second semiconductor layer and the third semiconductor layer.

18. The device according to claim 7, wherein the second insulating film is made of one of SiN, Al₂O₃, and HfO₂.