Semiconductor Device and Method of Forming Cavity Adjacent to Sensitive Region of Semiconductor Die Using Wafer-Level Underfill Material

• US 20110187005A1
• Filed: 02/03/2010
• Published: 08/04/2011
• Est. Priority Date: 02/03/2010
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Pagaila, Reza A.
• Granted Patent: US 8,574,960 B2
• Time in Patent Office: Days
• US Class Current: 257/777
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/315 the encapsulation having a cavity
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die with a stress sensitive region;

forming a masking layer over the stress sensitive region;

depositing underfill material over the semiconductor wafer, the masking layer preventing formation of the underfill material adjacent to the stress sensitive region;

removing the masking layer leaving a cavity in the underfill material adjacent to the stress sensitive region; and

singulating the semiconductor wafer into the first semiconductor die.

2. The method of claim 1, further including:

forming an interconnect structure; and

mounting the first semiconductor die to the interconnect structure with the cavity separating the stress sensitive region and interconnect structure.

3. The method of claim 1, further including mounting a second semiconductor die to the first semiconductor die with the cavity separating the stress sensitive region and second semiconductor die.

4. The method of claim 3, further including forming an interconnect structure over the second semiconductor die.

5. The method of claim 4, further including:

forming a bond wire between the second semiconductor die and interconnect structure; and

depositing an encapsulant over the first and second semiconductor die, interconnect structure, and bond wire.

6. The method of claim 3, further including forming an interconnect structure between the first semiconductor die and second semiconductor die.

7. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of first semiconductor die with a stress sensitive region;

forming a screen over the stress sensitive region;

depositing underfill material over the semiconductor wafer, the screen preventing formation of the underfill material adjacent to the stress sensitive region;

removing the screen leaving a cavity in the underfill material adjacent to the stress sensitive region; and

singulating the semiconductor wafer into the first semiconductor die.

8. The method of claim 7, further including:

forming an interconnect structure; and

mounting the first semiconductor die to the interconnect structure with the cavity separating the stress sensitive region and interconnect structure.

9. The method of claim 7, further including mounting a second semiconductor die to the first semiconductor die with the cavity separating the stress sensitive region and second semiconductor die.

10. The method of claim 9, further including forming an interconnect structure over the second semiconductor die.

11. The method of claim 10, further including:

forming a bond wire between the second semiconductor die and interconnect structure; and

depositing an encapsulant over the first and second semiconductor die, interconnect structure, and bond wire.

12. The method of claim 7, further including forming a conductive via through the first semiconductor die or second semiconductor die.

13. The method of claim 7, further including forming an interconnect structure between the first semiconductor die and second semiconductor die.

14. A method of manufacturing a semiconductor device, comprising:

providing a first semiconductor die with a stress sensitive region;

providing a second semiconductor die;

depositing underfill material over the first semiconductor die or second semiconductor die with a cavity in the underfill material adjacent to the stress sensitive region; and

mounting the first semiconductor die to the second semiconductor die with the cavity separating the stress sensitive region and second semiconductor die.

15. The method of claim 14, further including:

forming an interconnect structure; and

mounting the first semiconductor die to the interconnect structure.

16. The method of claim 14, further including forming an interconnect structure over the second semiconductor die.

17. The method of claim 16, further including:

forming a bond wire between the second semiconductor die and interconnect structure; and

depositing an encapsulant over the first and second semiconductor die, interconnect structure, and bond wire.

18. The method of claim 14, further including forming a conductive via through the first semiconductor die.

19. The method of claim 14, further including forming an interconnect structure between the first semiconductor die and second semiconductor die.

20. A semiconductor device, comprising:

a first semiconductor die with a stress sensitive region;

a second semiconductor die; and

an underfill material deposited over the first semiconductor die or second semiconductor die with a cavity in the underfill material adjacent to the stress sensitive region, the first semiconductor die being mounted to the second semiconductor die with the cavity separating the stress sensitive region and second semiconductor die.

21. The semiconductor device of claim 20, further including an interconnect structure, the first semiconductor die being mounted to the interconnect structure.

22. The semiconductor device of claim 20, further including an interconnect structure, the second semiconductor die being mounted to the interconnect structure.

23. The semiconductor device of claim 22, further including:

a bond wire formed between the second semiconductor die and interconnect structure; and

an encapsulant deposited over the first and second semiconductor die, interconnect structure, and bond wire.

24. The semiconductor device of claim 20, further including a conductive via formed through the first semiconductor die.

25. The semiconductor device of claim 20, further including an interconnect structure formed between the first semiconductor die and second semiconductor die.