Memory architectures and techniques to enhance throughput for cross-point arrays

• US 20110188282A1
• Filed: 02/02/2010
• Published: 08/04/2011
• Est. Priority Date: 02/02/2010
• Status: Active Grant

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Siau, Chang Hua, Namala, Sri, Eggleston, David, Chevallier, Christophe J.
• Granted Patent: US 8,638,584 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.

Claims

1. An integrated circuit comprising:

a substrate including a surface area;

a logic layer including active circuitry fabricated on the substrate;

memory elements electrically coupled with the active circuitry, the memory elements are fabricated directly above the logic layer within a boundary in a plane parallel to the substrate and array lines associated with subsets of the memory elements; and

a plurality of array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the memory elements,

wherein a quantity of memory elements in the subsets of the memory elements are configured to provide a throughput value.

2. The integrated circuit of claim 1, wherein the throughput value is configured to vary as a function of the quantity of memory elements independent of a die size for the substrate.

3. The integrated circuit of claim 1, wherein the plurality of array line decoders and the boundary define a first area and a second area, respectively, at least a portion of the second area overlapping at least a portion of the first area.

4. The integrated circuit of claim 1 and further comprising:

a plurality of arrays constituting an amount of memory and wherein each array includes a size configured to provide for the throughput value.

5. The integrated circuit of claim 1, wherein the memory elements are positioned in at least one layer of a two-terminal cross-point memory array that is positioned over the logic layer and in contact with the substrate.

6. The integrated circuit of claim 4, wherein the plurality of array line decoders are configured to access a subset of the plurality of arrays concurrently to communicate data at a first throughput value.

7. The integrated circuit of claim 6, wherein the first throughput value is a function of the size of each of the plurality of arrays, and

wherein the surface area of the substrate is independent of the size of each of the plurality of arrays.

8. The integrated circuit of claim 6, wherein the first throughput value is greater than a second throughput value, and

wherein the plurality of array line decoders and the memory elements provide the second throughput value, the memory elements being formed in a common plane, and the plurality of array line decoders and the memory elements having a planar surface area equivalent to the surface area.

9. The integrated circuit of claim 6, wherein the arrays each comprise a number of memory elements configured to determine a decoder area for a corresponding array line decoder, and

wherein an aggregate decoder area including the decoder areas for the plurality of array line decoders is no greater than an area determined by dimensions of the boundary.

10. The integrated circuit of claim 1 and further comprising:

a cross point memory array including

X-lines,

Y-lines, of which at least one Y-line is coupled with a group of the X lines, and

a subset of the memory elements being disposed between a subset of the X-lines and a subset of the Y lines.

11. The integrated circuit of claim 10, wherein the group of the subset of the memory elements constitute an array.

12. The integrated circuit of claim 1, wherein the memory elements comprise two-terminal memory elements each having a programmable resistivity to store a state as a value of resistance.

13. The integrated circuit of claim 12, wherein each two-terminal memory element includes an electrolytic insulator including a thickness that is less than approximately 50 Å

and at least one layer of a conductive oxide material in contact with the electrolytic insulator.

14. The integrated circuit of claim 1, wherein the active circuitry includes an interface configured as either a DRAM interface, a NAND interface, or a NOR interface.

15. A non-volatile memory device comprising:

a substrate having a die size;

a logic layer including active circuitry fabricated on the substrate; and

arrays positioned above the logic layer within an area in a plane parallel to the substrate, the arrays in electrical communication with the active circuitry, each of the arrays including

a quantity of memory elements, and

a quantity of decoders disposed between the substrate and the arrays, wherein the die size is independent of the quantity of decoders for a range of decoder quantities.

16. The non-volatile memory device of claim 15, wherein a ratio between the area and the die size is relatively constant for a reduced size for each of the arrays.

17. The non-volatile memory device of claim 16, wherein the reduced size includes fewer memory elements than in the quantity of memory elements.

18. The non-volatile memory device of claim 17, wherein the decoders are configured to access a subset of the arrays in parallel to access data at an enhanced throughput value corresponding to the reduced size, the enhanced throughput value being greater than a throughput value associated with each of the arrays having the quantity of memory elements.

19. The non-volatile memory device of claim 17, wherein the ratio is greater than another ratio between a combined area and the die size, the combined area composed of separate areas for the arrays and the quantity of decoders.

20. The non-volatile memory device of claim 16, wherein the decoders are configured to access a subset of the arrays in parallel to access data at a throughput value greater than 50 megabytes per second.

21. The non-volatile memory device of claim 16 and further comprising:

a quantity of the arrays greater than 64 arrays.

22. A method for fabricating a non-volatile memory device, comprising:

identifying a region on a substrate;

forming in the region a quantity of array line decoders, the quantity of the array line decoders being a function of a size for each of a quantity of arrays; and

forming the quantity of arrays substantially over the quantity of array line decoders,

wherein the size for each of the arrays is configured to provide for a throughput value.

23. The method of claim 22 and further comprising:

determining a range of areas in which a value of die efficiency for the non-volatile memory device is independent of the quantity of array line decoders;

determining a range of throughput values associated with the value of die efficiency; and

selecting the throughput value from the range of throughput values.

24. The method of claim 22 and further comprising:

forming peripheral circuit elements in the region to increase die efficiency for the non-volatile memory device.

25. The method of claim 24, wherein the peripheral circuit elements include pass gates and control lines.

26. The method of claim 22 and further comprising:

forming a cross point memory array over the region, the forming including

fabricating X-lines,

fabricating Y-lines, and

fabricating groups of Y-line portions, each Y-line portion arranged electrically in parallel with each other within the groups; and

disposing memory elements in the arrays, each of which includes a subset of the X-lines and a group of the Y-line portions.

27. The method as set forth in claim 26, wherein forming the cross point memory array comprises forming at least one of the Y-line portions in two or more layers of memory.

28. The method as set forth in claim 26 and further comprising.

disposing the X-lines and the Y-lines substantially parallel to an X-Y plane;

and

disposing the Y-line portions substantially parallel to a Y-Z plane.