Semiconductor Memory Device and Semiconductor Device

• US 20110188296A1
• Filed: 04/14/2011
• Published: 08/04/2011
• Est. Priority Date: 06/29/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Fujita, Masashi
• Granted Patent: US 8,259,487 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G11C 15/04 using semiconductor elements
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

The semiconductor memory device includes an initialization memory cell having a first inverter circuit including a first transistor and a second transistor, and a second inverter circuit whose input portion is connected to an output portion of the first inverter circuit and output portion is connected to an input portion of the first inverter circuit, and including a third transistor and a fourth transistor. An absolute value of a threshold voltage of the third transistor is smaller than that of the first transistor.

Claims

1-15. -15. (canceled)

16. A semiconductor memory device comprising:

a plurality of data hold memory cells;

an initialization memory cell;

a first data line;

a second data line; and

a word line,

wherein each of the plurality of data hold memory cells and the initialization memory cell comprises;

a first inverter circuit comprising a first transistor;

a second inverter circuit comprising a second transistor;

a third transistor; and

a fourth transistor,

wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor,

wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line,

wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line,

wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell and

wherein the plurality of data hold memory cells and the initialization memory cell are connected through the word line.

23. The semiconductor memory device according to claim 16,

wherein one of the first transistor and the second transistor comprises a substrate terminal adjacent to a semiconductor layer of the one of the first transistor and the second transistor with a gate insulating layer therebetween, and

wherein the substrate terminal is supplied with a voltage for controlling a threshold voltage of the one of the first transistor and the second transistor.

27. The semiconductor memory device according to claim 16, wherein the semiconductor memory device is incorporated into a semiconductor device as a first memory device,

wherein the semiconductor device further comprises:

a CPU including an arithmetic unit, and

a second memory device,

wherein the second memory device is a main memory device, and

wherein the first memory device is a subordinate memory device.

31. The semiconductor memory device according to claim 16, further comprising:

a power supply line;

a ground line;

a fifth transistor;

a resistor; and

a capacitor,

wherein the power supply line is electrically connected to the first transistor and the second transistor,

wherein a gate terminal of the fifth transistor is electrically connected to the power supply line through the resistor, and

wherein the gate terminal of the fifth transistor is electrically connected to the ground line through the capacitor.

17. A semiconductor memory device comprising:

a plurality of data hold memory cells;

an initialization memory cell;

a first data line;

a second data line; and

a word line,

wherein each of the plurality of data hold memory cells and the initialization memory cell comprises;

a first inverter circuit comprising a first transistor;

a second inverter circuit comprising a second transistor;

a third transistor; and

a fourth transistor,

wherein the word line is electrically connected to a gate electrode of the third transistor and a gate electrode of the fourth transistor,

wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and the second data line,

wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line,

wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor,

wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and

wherein the plurality of data hold memory cells and the initialization memory cell are connected through the word line.

20. The semiconductor memory device according to claim 17,

wherein the thickness of the semiconductor layer of the first transistor is more than or equal to quarter and less than or equal to half a channel length of the first transistor, and

wherein the thickness of the semiconductor layer of the second transistor is more than or equal to half a channel length of the second transistor.

24. The semiconductor memory device according to claim 17,

wherein one of the first transistor and the second transistor comprises a substrate terminal adjacent to the semiconductor layer of the one of the first transistor and the second transistor with a gate insulating layer therebetween, and

wherein the substrate terminal is supplied with a voltage for controlling a threshold voltage of the one of the first transistor and the second transistor.

28. The semiconductor memory device according to claim 17, wherein the semiconductor memory device is incorporated into a semiconductor device as a first memory device,

wherein the semiconductor device further comprises:

a CPU including an arithmetic unit, and

a second memory device,

wherein the second memory device is a main memory device, and

wherein the first memory device is a subordinate memory device.

32. The semiconductor memory device according to claim 17, further comprising:

a power supply line;

a ground line;

a fifth transistor;

a resistor; and

a capacitor,

wherein the power supply line is electrically connected to the first transistor and the second transistor,

wherein a gate terminal of the fifth transistor is electrically connected to the power supply line through the resistor, and

wherein the gate terminal of the fifth transistor is electrically connected to the ground line through the capacitor.

18. A semiconductor memory device comprising:

a plurality of data hold memory cells;

an initialization memory cell;

a first data line;

a second data line;

a third data line;

a word line; and

a ground line,

wherein each of the plurality of data hold memory cells and the initialization memory cell comprises;

a first inverter circuit comprising a first transistor;

a second inverter circuit comprising a second transistor;

a third transistor electrically connected to the ground line; and

a fourth transistor electrically connected to the third transistor, wherein a gate electrode of the fourth transistor is electrically connected to the word line,

wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit, the second data line, and a gate electrode of the third transistor,

wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line,

wherein the second inverter circuit is electrically connected to the third data line through the third transistor and the fourth transistor,

wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor, and

wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and

wherein the plurality of data hold memory cells and the initialization memory cell are connected through the word line.

21. The semiconductor memory device according to claim 18,

wherein the thickness of the semiconductor layer of the first transistor is more than or equal to quarter and less than or equal to half a channel length of the first transistor, and

wherein the thickness of the semiconductor layer of the second transistor is more than or equal to half a channel length of the second transistor.

25. The semiconductor memory device according to claim 18,

wherein one of the first transistor and the second transistor comprises a substrate terminal adjacent to the semiconductor layer of the one of the first transistor and the second transistor with a gate insulating layer therebetween, and

wherein the substrate terminal is supplied with a voltage for controlling a threshold voltage of the one of the first transistor and the second transistor.

29. The semiconductor memory device according to claim 18, wherein the semiconductor memory device is incorporated into a semiconductor device as a first memory device,

wherein the semiconductor device further comprises:

a CPU including an arithmetic unit, and

a second memory device,

wherein the second memory device is a main memory device, and

wherein the first memory device is a subordinate memory device.

33. The semiconductor memory device according to claim 18, further comprising:

a power supply line;

a fifth transistor;

a resistor; and

a capacitor,

wherein a gate terminal of the fifth transistor is electrically connected to the power supply line through the resistor, and

wherein the gate terminal of the fifth transistor is electrically connected to the ground line through the capacitor.

19. A semiconductor memory device comprising:

a plurality of data hold memory cells;

an initialization memory cell;

a first data line;

a second data line;

a third data line;

a word line; and

a power supply line,

wherein each of the plurality of data hold memory cells and the initialization memory cell comprises;

a first inverter circuit comprising a first transistor, wherein the first inverter circuit is electrically connected to the power supply line;

a second inverter circuit comprising a second transistor, wherein the second inverter circuit is electrically connected to the power supply line;

a third transistor; and

a fourth transistor electrically connected to the third transistor, wherein a gate electrode of the fourth transistor is electrically connected to the word line,

wherein an input terminal of the first inverter circuit is electrically connected to an output terminal of the second inverter circuit and a gate electrode of the third transistor,

wherein an output terminal of the first inverter circuit is electrically connected to an input terminal of the second inverter circuit and the first data line,

wherein the second data line is electrically connected to the input terminal of the first inverter circuit and the output terminal of the second inverter circuit,

wherein the power supply line is electrically connected to the third data line through the third transistor and the fourth transistor,

wherein a thickness of a semiconductor layer of the first transistor is more than a thickness of a semiconductor layer of the second transistor, and

wherein an absolute value of a threshold voltage of the second transistor is smaller than an absolute value of a threshold voltage of the first transistor in the initialization memory cell, and

wherein the plurality of data hold memory cells and the initialization memory cell are connected through the word line.

22. The semiconductor memory device according to claim 19,

wherein the thickness of the semiconductor layer of the first transistor is more than or equal to quarter and less than or equal to half a channel length of the first transistor, and

wherein the thickness of the semiconductor layer of the second transistor is more than or equal to half a channel length of the second transistor.

26. The semiconductor memory device according to claim 19,

wherein one of the first transistor and the second transistor comprises a substrate terminal adjacent to the semiconductor layer of the one of the first transistor and the second transistor with a gate insulating layer therebetween, and

wherein the substrate terminal is supplied with a voltage for controlling a threshold voltages of the one of the first transistor and the second transistor.

30. The semiconductor memory device according to claim 19, wherein the semiconductor memory device is incorporated into a semiconductor device as a first memory device,

wherein the semiconductor device further comprises:

a CPU including an arithmetic unit, and

a second memory device,

wherein the second memory device is a main memory device, and

wherein the first memory device is a subordinate memory device.

34. The semiconductor memory device according to claim 19, further comprising:

a ground line;

a fifth transistor;

a resistor; and

a capacitor,

wherein a gate terminal of the fifth transistor is electrically connected to the power supply line through the resistor, and

wherein the gate terminal of the fifth transistor is electrically connected to the ground line through the capacitor.