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METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS

  • US 20110188312A1
  • Filed: 04/08/2011
  • Published: 08/04/2011
  • Est. Priority Date: 05/27/2008
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • an array of memory cells including a number of data cells and a number of reference cells; and

    control circuitry coupled to the array of memory cells and configured to;

    as a part of an erase operation performed on a selected group of memory cells, perform a programming monitor operation on the number of reference cells prior to performing a programming operation on at least some of the number of data cells; and

    at least partially based on the programming monitor operation, adjusting voltages associated with operating the at least some of the number of data cells.

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