SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE
First Claim
1. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:
- an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs;
a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets;
a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port;
a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and
a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage.
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Accused Products
Abstract
A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit.
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Citations
1 Claim
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1. A system for transmitting data packets from a memory hub to a memory controller over an upstream link, comprising:
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an upstream reception port coupled to the upstream link and operable to receive data packets from downstream memory hubs; a bypass bus coupled to the upstream reception port and operable to receive the data packets from the upstream reception port and to transport the data packets; a temporary storage coupled to the upstream reception port and operable to receive the data packets from the upstream reception port; a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus; and a breakpoint logic circuit coupled to the bypass multiplexer and operable to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage.
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Specification