MULTICORE PROCESSOR AND ONBOARD ELECTRONIC CONTROL UNIT USING SAME

• US 20110191620A1
• Filed: 01/03/2011
• Published: 08/04/2011
• Est. Priority Date: 02/01/2010
• Status: Active Grant

• Current Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Original Assignee: DENSO Corporation, Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: Arai, Soichiro, WAKABAYASHI, Tetsuaki
• Granted Patent: US 9,222,430 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: F02D 41/26 using computer, e.g. microprocessor
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.

Claims

1. A multicore processor comprising:

a plurality of cores, wherein;

the plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period; and

a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.

2. The multicore processor according to claim 1, wherein:

the number of the plurality of cores is an integer and is equal to or greater than 2; and

the variation phase of a frequency of the operation clock of each core is shifted by a phase corresponding to a time that is obtained by dividing the period by the number of the plurality of cores.

3. The multicore processor according to claim 1, wherein:

a central frequency during the variations of a frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores; and

a variation amplitude of a frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores.

4. The multicore processor according to claim 1, wherein a variation mode of a frequency of the operation clock of each core of the plurality of cores is the same among the plurality of cores.

5. The multicore processor according to claim 1, wherein a shift amount of the variation phase of a frequency of the operation clock among the cores during operation is changed in accordance with an operational condition of the plurality of cores.

6. An onboard electronic control unit comprising:

a multicore processor having a plurality of cores, wherein

a plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.