Detection And Diagnosis Of Scan Cell Internal Defects

• US 20110191643A1
• Filed: 02/23/2009
• Published: 08/04/2011
• Est. Priority Date: 02/21/2008
• Status: Active Grant

• Current Assignee: Siemens Industry Software Inc. (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Huang, Yu, Lai, Liyang, Guo, Ruifeng, Cheng, Wu-Tung
• Granted Patent: US 9,086,459 B2
• Time in Patent Office: Days
• US Class Current: 714/703
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318583 Design for test
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models.

Claims

1-6. -6. (canceled)

7. A method of scan cell internal defect diagnosis, comprising:

identifying a failing scan chain;

determining an upper bound and a lower bound of candidate scan cells in the failing scan chain; and

identifying one or more scan cell internal fault candidates in the candidate scan cells based on a failure log and failing scan test patterns associated with the failure log.

8. The method recited in claim 7, further comprising:

performing a diagnostic simulation process for the one or more scan cell internal fault candidates.

9. The method recited in claim 8, further comprising:

ranking the one or more scan cell internal fault candidates based on results of the diagnostic simulation process.

10. The method recited in claim 7, wherein the identifying a failing scan chain is based on applying one or more scan test patterns, or one or more chain test patterns, or both.

11. The method recited in claim 7, wherein the identifying one or more scan cell internal fault candidates comprises:

selecting a candidate scan cell from the candidate scan cells;

determining whether the candidate scan cell has a same output value for identical input combinations based on a failure log and failing scan test patterns associated with the failure log.

12. The method recited in claim 11, wherein the identifying one or more scan cell internal fault candidates further comprises:

repeating the selecting and the determining until all of the candidate scan cells are selected.

13. The method recited in claim 11, wherein the determining whether the candidate scan cell has a same output value for identical input combinations comprises:

changing scan load values of the candidate scan cell and downstream scan cells to Xs; and

performing a simulation process using one or more of the failing scan test patterns to determine input combinations of the candidate scan cell during various unload shift cycles.

14. A processor-readable medium storing processor-executable instructions for causing one or more processors to perform a method of scan cell internal defect diagnosis, the method comprising:

identifying a failing scan chain;

determining an upper bound and a lower bound of candidate scan cells in the failing scan chain; and

identifying one or more scan cell internal fault candidates in the candidate scan cells based on a failure log and failing scan test patterns associated with the failure log.

15. The processor-readable medium recited in claim 14, wherein the method further comprises:

performing a diagnostic simulation process for the one or more scan cell internal fault candidates.

16. The processor-readable medium recited in claim 15, wherein the method further comprises:

ranking the one or more scan cell internal fault candidates based on results of the diagnostic simulation process.

17. The processor-readable medium recited in claim 14, wherein the identifying a failing scan chain is based on applying one or more scan test patterns, or one or more chain test patterns, or both.

18. The processor-readable medium recited in claim 14, wherein the identifying one or more scan cell internal fault candidates comprises:

selecting a candidate scan cell from the candidate scan cells;

determining whether the candidate scan cell has a same output value for identical input combinations based on a failure log and failing scan test patterns associated with the failure log.

19. The processor-readable medium recited in claim 18, wherein the identifying one or more scan cell internal fault candidates further comprises:

repeating the selecting and the determining until all of the candidate scan cells are selected.

20. The processor-readable medium recited in claim 18, wherein the determining whether the candidate scan cell has a same output value for identical input combinations comprises:

changing scan load values of the candidate scan cell and downstream scan cells to Xs; and

performing a simulation process using one or more of the failing scan test patterns to determine input combinations of the candidate scan cell during various unload shift cycles.