METHOD OF FABRICATING VERTICAL STRUCTURE LEDS

• US 20110193128A1
• Filed: 03/14/2011
• Published: 08/11/2011
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Lee, Jong Lam, Yoo, Myung C., Jeong, In-Kwon
• Granted Patent: US 8,384,120 B2
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: H01C 7/006 Thin film resistors
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 33/0025 comprising only AIIIBV compounds
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: Y10S 438/958 Passivation layer
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method of fabricating semiconductor devices, such as GaN LEDs, on insulating substrates, such as sapphire. Semiconductor layers are produced on the insulating substrate using normal semiconductor processing techniques. Trenches that define the boundaries of the individual devices are then formed through the semiconductor layers and into the insulating substrate, beneficially by using inductive coupled plasma reactive ion etching. The trenches are then filled with an easily removed layer. A metal support structure is then formed on the semiconductor layers (such as by plating or by deposition) and the insulating substrate is removed. Electrical contacts, a passivation layer, and metallic pads are then added to the individual devices, and the individual devices are then diced out.

Claims

1-42. -42. (canceled)

43. A semiconductor light-emitting device, comprising:

a conductive support structure;

a semiconductor structure over the conductive support structure, the semiconductor structure having a first surface, a second surface, and a side surface, wherein the semiconductor structure comprises a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, wherein the second surface is opposite the first surface, and wherein the first surface, relative to the second surface, is proximate to the conductive support structure;

a first electrode electrically connected to the first-type semiconductor layer, wherein the first electrode is arranged between the conductive support structure and the first surface of the semiconductor structure, and wherein the first-type electrode comprises a first metallic layer and a second metallic layer on the first metallic layer;

a second electrode electrically connected to the second-type semiconductor layer, the second electrode comprising a third metallic layer and a fourth metallic layer on the third metallic layer; and

a passivation layer contacting the second surface and the side surface of the semiconductor structure, wherein the portion of the passivation layer that contacts the second surface is arranged over the conductive support structure, wherein the passivation layer has a first length in contact with the first-type semiconductor layer and a second length in contact with the second-type semiconductor layer, and wherein the second length is greater than the first length.

44. The device according to claim 43, wherein the first metallic layer comprises Au or the second metallic layer comprises one of Pt, Pd, Ru, Ni, Cr, or ITO.

45. The device according to claim 43, wherein the third metallic layer comprises Ti or the fourth metallic layer comprises Al.

46. The device according to claim 43, wherein the passivation layer is further arranged over the first surface of the semiconductor structure.

47. The device according to claim 43, wherein the first metallic layer has a first width and the second metallic layer has a second width, and wherein the first width and the second width are substantially the same.

48. The device according to claim 43, wherein the second electrode is arranged over the second surface of the semiconductor structure.

49. The device according to claim 48, wherein the passivation layer is arranged over a part of the second electrode.

50. The device according to claim 43, wherein the passivation layer contacting the side surface of the semiconductor structure extends to the second surface of the semiconductor structure.

51. The device according to claim 43, wherein the conductive support structure comprises a metal layer.

52. The device according to claim 51, wherein the metal layer comprises one of Cu, Cr, Ni, Au, Ag, Mo, Pt, Pd, W, and Al.

53. The device according to claim 43, wherein the first-type semiconductor layer is a p-type layer and the second-type semiconductor layer is an n-type layer.

54. The device according to claim 43, wherein the passivation layer is further arranged partially between the conductive support structure and the semiconductor structure.

55. The device according to claim 43, wherein the first electrode contacts the first surface of the semiconductor structure, and wherein a contact area between the first electrode and the first surface of the semiconductor structure is smaller than the entire area of the first surface of the semiconductor structure.

56. A semiconductor light-emitting device, comprising:

a conductive support structure;

a semiconductor structure over the conductive support structure, the semiconductor structure having a first surface, a second surface, and a side surface, wherein the semiconductor structure comprises a first-type semiconductor layer, an active layer, and a second-type semiconductor layer, wherein the second surface is opposite the first surface, and wherein the first surface, relative to the second surface, is proximate to the conductive support structure;

a first electrode electrically connected to the first-type semiconductor layer, wherein the first electrode is arranged between the conductive support structure and the first surface of the semiconductor structure, and wherein the first-type electrode comprises a first metallic layer and a second metallic layer on the first metallic layer;

a second electrode electrically connected to the second-type semiconductor layer, the second electrode comprising a third metallic layer and a fourth metallic layer on the third metallic layer;

a passivation layer contacting the second surface and the side surface of the semiconductor structure, wherein the passivation layer has a first length in contact with the first-type semiconductor layer and a second length in contact with the second-type semiconductor layer, and wherein the second length is greater than the first length; and

a metallic pad over the second electrode, wherein the metallic pad is arranged higher than the portion of the passivation layer contacting the second surface.

57. The device according to claim 56, wherein the second electrode and the metallic pad have surfaces that contact each other, wherein the second electrode has a third length facing the metallic pad and a fourth length in contact with the metallic pad, and wherein the third length is different from the fourth length.

58. The device according to claim 56, wherein the passivation layer is further arranged partially between the conductive support structure and the semiconductor structure.

59. The device according to claim 58, wherein the passivation layer arranged partially between the conductive support structure and the semiconductor structure extends to the portion of the passivation layer contacting the second surface.

60. The device according to claim 58, wherein a width of the passivation layer arranged partially between the conductive support structure and the semiconductor structure is different from a width of the passivation layer contacting the second surface.

61. The device according to claim 56, wherein the metallic pad comprises at least one of Cr and Au.

62. The device according to claim 56, wherein the metallic pad is arranged higher than the portion of the passivation layer contacting the second surface.