FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE

• US 20110193182A1
• Filed: 01/26/2011
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: TAKEMURA, Yasuhiko
• Granted Patent: US 8,436,431 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.

Claims

1. A field effect transistor comprising:

a semiconductor layer;

a first conductor electrode and a second conductor electrode which are provided in contact with one surface of the semiconductor layer; and

a gate provided on the other surface side of the semiconductor layer,

wherein an offset region is formed in at least one of a region between the first conductor electrode and the gate and a region between the second conductor electrode and the gate, and

wherein a bandgap of the semiconductor layer is greater than or equal to 2 electron volts and less than 4 electron volts.

6. The field effect transistor according to claim 1, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

11. The field effect transistor according to claim 1, wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

16. The field effect transistor according to claim 1, further comprising a gate insulating film between the semiconductor layer and the gate.

21. The field effect transistor according to claim 1, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

26. The field effect transistor according to claim 1, wherein a width of the offset region is more than or equal to 10 nm and less than or equal to 100 nm.

31. The field effect transistor according to claim 1, wherein the semiconductor layer comprises an i-type semiconductor.

36. The field effect transistor according to claim 1, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

2. A field effect transistor comprising:

a semiconductor layer;

a first conductor electrode and a second conductor electrode which are provided in contact with one surface of the semiconductor layer; and

a gate provided on the other surface side of the semiconductor layer,

wherein an offset region is formed in at least one of a region between the first conductor electrode and the gate and a region between the second conductor electrode and the gate.

7. The field effect transistor according to claim 2, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

12. The field effect transistor according to claim 2, wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

17. The field effect transistor according to claim 2, further comprising a gate insulating film between the semiconductor layer and the gate.

22. The field effect transistor according to claim 2, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

27. The field effect transistor according to claim 2, wherein a width of the offset region is more than or equal to 10 nm and less than or equal to 100 nm.

32. The field effect transistor according to claim 2, wherein the semiconductor layer comprises an i-type semiconductor.

37. The field effect transistor according to claim 2, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

3. A field effect transistor comprising:

a semiconductor layer;

a first conductor electrode and a second conductor electrode provided in contact with one surface of the semiconductor layer; and

a gate provided over the same surface,

wherein an offset region is formed in at least one of a region between the first conductor electrode and the gate and a region between the second conductor electrode and the gate.

8. The field effect transistor according to claim 3, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

13. The field effect transistor according to claim 3, wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

18. The field effect transistor according to claim 3, further comprising a gate insulating film between the semiconductor layer and the gate.

23. The field effect transistor according to claim 3, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

28. The field effect transistor according to claim 3, wherein a width of the offset region is more than or equal to 10 nm and less than or equal to 100 nm.

33. The field effect transistor according to claim 3, wherein the semiconductor layer comprises an i-type semiconductor.

38. The field effect transistor according to claim 3, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

4. A semiconductor device comprising:

a semiconductor layer;

a first conductor electrode, a second conductor electrode, and a third conductor electrode which are provided in contact with one surface of the semiconductor layer; and

a gate provided on the other surface side of the semiconductor layer,

wherein the gate overlaps with at least part of a region between the first conductor electrode and the second conductor electrode, and

wherein the gate does not overlap with a region between the second conductor electrode and the third conductor electrode.

9. The semiconductor device according to claim 4, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

14. The semiconductor device according to claim 4, wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

19. The semiconductor device according to claim 4, further comprising a gate insulating film between the semiconductor layer and the gate.

24. The semiconductor device according to claim 4, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

29. The semiconductor device according to claim 4, wherein a width of a first portion of the semiconductor layer between the first conductor electrode and the second conductor electrode is wider than that of a second portion of the semiconductor layer between the second conductor electrode and the third conductor electrode.

34. The semiconductor device according to claim 4, wherein the semiconductor layer comprises an i-type semiconductor.

39. The semiconductor device according to claim 4, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

41. The semiconductor device according to claim 4, wherein the semiconductor device is an inverter.

5. A semiconductor device comprising:

a semiconductor layer;

a first conductor electrode, a second conductor electrode, and a third conductor electrode which are provided in contact with one surface of the semiconductor layer; and

a gate provided over the same surface of the semiconductor layer,

wherein the gate overlaps with at least part of a region between the first conductor electrode and the second conductor electrode, and

wherein the gate does not overlap with a region between the second conductor electrode and the third conductor electrode.

10. The semiconductor device according to claim 5, wherein a portion of the first conductor electrode and a portion of the second conductor electrode which are in contact with the semiconductor layer have a work function lower than a sum of an electron affinity of the semiconductor layer and 0.3 electron volts.

15. The semiconductor device according to claim 5, wherein an ohmic junction is formed between the semiconductor layer and the first conductor electrode and between the semiconductor layer and the second conductor electrode.

20. The semiconductor device according to claim 5, further comprising a gate insulating film between the semiconductor layer and the gate.

25. The semiconductor device according to claim 5, wherein a work function of a portion of the gate which is the closest to the semiconductor layer is higher than a sum of an electron affinity of the semiconductor layer and 0.6 electron volts.

30. The semiconductor device according to claim 5, wherein a width of a first portion of the semiconductor layer between the first conductor electrode and the second conductor electrode is wider than that of a second portion of the semiconductor layer between the second conductor electrode and the third conductor electrode.

35. The semiconductor device according to claim 5, wherein the semiconductor layer comprises an i-type semiconductor.

40. The semiconductor device according to claim 5, wherein the gate comprises a material selected from the group consisting of platinum, gold, tungsten, and indium nitride.

42. The semiconductor device according to claim 5, wherein the semiconductor device is an inverter.