STRUCTURE AND METHOD FOR MAKING CRACK STOP FOR 3D INTEGRATED CIRCUITS
First Claim
Patent Images
1. A structure comprising:
- a first component having a first semiconductor substrate and a first layer with first metallization formed therein, said first component having a first annular region peripheral to a first active region;
a second component having a second semiconductor substrate and a second layer with second metallization formed therein;
a bonding layer whereby said second component is bonded to said first component to form a bonded structure having a composite active area and a periphery; and
a circumferential wall adjacent to said periphery, said circumferential wall formed through said bonding layer.
6 Assignments
0 Petitions
Accused Products
Abstract
A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.
93 Citations
20 Claims
-
1. A structure comprising:
-
a first component having a first semiconductor substrate and a first layer with first metallization formed therein, said first component having a first annular region peripheral to a first active region; a second component having a second semiconductor substrate and a second layer with second metallization formed therein; a bonding layer whereby said second component is bonded to said first component to form a bonded structure having a composite active area and a periphery; and a circumferential wall adjacent to said periphery, said circumferential wall formed through said bonding layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A structure comprising:
-
a first component having a first semiconductor substrate and a first layer having first metallization formed therein; a second component bonded to said first component, said second component having a thinned semiconductor substrate, said thinned semiconductor substrate having a periphery and an active region within an annular inactive region, said annular inactive region adjacent to said periphery; and a circumferential wall formed through said thinned semiconductor substrate and within said annular inactive region such that a straight line through said periphery into said active region necessarily intersects said circumferential wall.
-
-
14. A method of forming a 3D IC comprising the steps of:
-
providing a bonded structure comprising a bonding layer whereby a first component is bonded to a second component, said first component having a first semiconductor substrate and a first layer with first metallization formed therein, said second component having a second semiconductor substrate and a second layer with second metallization formed therein, said second semiconductor substrate substantially thinner than said first semiconductor substrate, and said bonded structure having a periphery; and forming a circumferential wall through said bonding layer and adjacent to said periphery. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification