SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20110193203A1
• Filed: 02/02/2011
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: GOTO, Masakatsu, Enomoto, Minoru
• Granted Patent: US 8,377,752 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01064 : Gadolinium [Gd]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained.

Claims

1. A semiconductor device comprising:

(a) a multilayered wiring board having a first internal wiring and a second internal wiring formed in a layer above the first internal wiring; and

(b) a first semiconductor chip embedded inside the multilayered wiring board,

wherein the first semiconductor chip has;

(b1) bump electrodes formed over a main surface of the first semiconductor chip; and

(b2) an insulating film formed over a back surface, which is on the side opposite to the main surface, of the first semiconductor chip,

wherein the main surface of the first semiconductor chip is opposed to the side of the first internal wiring formed over the multilayered wiring board,

wherein the first internal wiring is coupled with the first semiconductor chip through the bump electrodes, and

wherein the back surface of the first semiconductor chip is insulated from the second internal wiring by the insulating film.

2. A semiconductor device according to claim 1,

wherein the second internal wiring is directly formed over the insulating film.

3. A semiconductor device according to claim 1,

wherein the insulating film is a die attach film.

4. A semiconductor device according to claim 1,

wherein the insulating film is a film made by curing a liquid resin.

5. A semiconductor device according to claim 1,

wherein the insulating film comprises an epoxy material.

6. A semiconductor device according to claim 1 further comprising:

a third internal wiring formed in a layer immediately above the second internal wiring,

wherein a film thickness of the insulating film is smaller than a thickness between the second internal wiring and the third internal wiring.

7. A semiconductor device according to claim 1,

wherein the bump electrode comprises a gold material.

8. A semiconductor device according to claim 1,

wherein the bump electrode comprises a solder material.

9. A semiconductor device according to claim 1,

wherein a through via is formed for coupling internal wirings of different layers in the multilayered wiring board.

10. A semiconductor device according to claim 9,

wherein the through via comprises stud bump electrodes.

11. A semiconductor device according to claim 10,

wherein the through via is formed by stacking the stud bump electrodes.

12. A semiconductor device according to claim 10,

wherein the stud bump electrode comprises a gold material.

13. A semiconductor device according to claim 1,

wherein the first semiconductor chip is surrounded by an electromagnetic shield.

14. A semiconductor device according to claim 1 further comprising:

a package body in which a second semiconductor chip is sealed,

wherein the package body is mounted over the multilayered wiring board.

15. A semiconductor device according to claim 1,

wherein the second semiconductor chip and passive parts are mounted over the multilayered board.

16. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor chip where a bump electrode is formed over a main surface and a thermosetting insulating film is formed over a back surface;

(b) preparing a base board which serves as a core of a multilayered wiring board and in which a first internal wiring is formed;

(c) applying a thermosetting resin to a chip mounting region of the base board;

(d) after the step (c), coupling the bump electrode formed over the semiconductor chip with the first internal wiring by mounting the semiconductor chip, while heating the semiconductor chip, in the chip mounting region of the base board through the thermosetting resin;

(e) after the step (d), applying a heat treatment;

(f) after the step (e), forming a first interlayer insulator so as to cover a side surface of the semiconductor chip and to allow the insulating film formed over the back surface, which is on an upper surface side of the semiconductor chip, to be exposed; and

(g) after the step (f), forming a second interlayer insulator covering from the first interlayer insulator to the semiconductor chip so that the conductive film may come in contact with the insulating film, the patterned conductive film being pasted to the upper part of the second interlayer insulator, and forming a second internal wiring comprising the conductive film so as to be directly in contact with the insulating film,

wherein, by being heated in the steps (d) and (e), in a stage before the step (g), the insulating film is more cured than the insulating film in the step (a).

17. A method of manufacturing a semiconductor device according to claim 16,

wherein the insulating film is a die attach film.

18. A method of manufacturing a semiconductor device according to claim 16,

wherein the insulating film comprises a liquid resin.

19. A method of manufacturing a semiconductor device according to claim 16,

wherein the bump electrode comprises a gold material.

20. A method of manufacturing a semiconductor device according to claim 16,

wherein the first interlayer insulator and the second interlayer insulator comprise prepreg, and

wherein the conductive film includes a copper film.

21. A method of manufacturing a semiconductor device according to claim 16,

wherein after the step (e), before the step (f), a stud bump electrode comprising a gold material is formed over the base board with use of a capillary, and

wherein, in the step (f), a through via comprising the stud bump electrode is formed in the first interlayer insulator by forming the first interlayer insulator so as to sandwich the stud bump electrode.

22. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor chip where a bump electrode is formed over a main surface and a thermosetting insulating film is formed over a back surface;

(b) preparing a base board which serves as a core of a multilayered wiring board and in which a first internal wiring is formed;

(c) coupling the bump electrode formed over the semiconductor chip with the first internal wiring by mounting the semiconductor chip in a chip mounting region of the base board;

(d) after the step (c), performing a reflow treatment which is a heat treatment;

(e) after the step (d), applying an underfill material into a gap between the semiconductor chip and the base board;

(f) after the step (e), applying a heat treatment;

(g) after the step (f), forming a first interlayer insulator so as to cover a side surface of the semiconductor chip and to allow the insulating film formed over the back surface, which is on an upper surface side of the semiconductor chip, to be exposed; and

(h) after the step (g), forming a second interlayer insulator covering from the first interlayer insulator to the semiconductor chip so that the conductive film may come in contact with the insulating film, the patterned conductive film being pasted to the upper part of the second interlayer insulator, and forming a second internal wiring comprising the conductive film so as to be directly in contact with the insulating film,

wherein, by being heated in the steps (d), (e), and (f), in a stage before the step (h), the insulating film is more cured than the insulating film in the step (a).

23. A method of manufacturing a semiconductor device according to claim 22,

wherein the insulating film is a die attach film.

24. A method of manufacturing a semiconductor device according to claim 22,

wherein the insulating film comprises a liquid resin.

25. A method of manufacturing a semiconductor device according to claim 22,

wherein the bump electrode comprises a solder material.

26. A method of manufacturing a semiconductor device according to claim 22,

wherein the first and second interlayer insulators comprise prepreg, and

wherein the conductive film includes a copper film.

27. A method of manufacturing a semiconductor device according to claim 22,

wherein after the step (f), before the step (g), a stud bump electrode is formed over the base board with use of a capillary, and

wherein, in the step (g), a through via comprising the stud bump electrode is formed in the first interlayer insulator by forming the first interlayer insulator so as to sandwich the stud bump electrode.