Systems and Methods Providing Arrangements of Vias

• US 20110193212A1
• Filed: 02/08/2010
• Published: 08/11/2011
• Est. Priority Date: 02/08/2010
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Lisk, Durodami J., Chandrasekaran, Arvind, Nowak, Matthew Michael, Gu, Shiqun, Ray, Urmi, Toms, Thomas R., Suh, Jungwon
• Application Number:
  US12/701,642
• Publication Number:
  US 20110193212A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05093 of a plurality of vias
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13028 the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14505 Bump connectors having different materials
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/17517 including bump connectors providing primarily mechanical support
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3677 : Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.

Claims

1. A semiconductor chip comprising:

an array of electrical contacts; and

a plurality of vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts, in which a first one of the electrical contacts of the array of electrical contacts is coupled to N vias of the plurality of vias, and in which a second one of the electrical contacts of the array of electrical contacts is coupled to M vias of the plurality of vias, where M and N are positive integers of different values.

2. The semiconductor chip of claim 1 in which the first electrical contact comprises a power contact, and in which the second electrical contact comprises a signal contact, and further in which M is larger than N.

3. The semiconductor chip of claim 1 in which the plurality of vias comprises at least one thermal via.

4. The semiconductor chip of claim 1 in which the plurality of vias comprises Through Silicon Vias (TSVs).

5. The semiconductor chip of claim 1 in which the N vias couple directly to the first electrical contact.

6. The semiconductor chip of claim 1 in which the N vias couple to the first electrical contact through a redistribution layer.

7. The semiconductor chip of claim 1 further comprising:

a plurality of support bumps outside of the array of electrical contacts, the support bumps providing mechanical support for a chip package that includes the semiconductor chip.

8. The semiconductor chip of claim 7 in which the first semiconductor chip comprises a logic chip that is coupled to a memory chip in the chip package.

9. The semiconductor chip of claim 1 in which the array of electrical contacts comprises:

a plurality of ground contacts;

a plurality of power contacts; and

a plurality of signal contacts, the plurality of power contacts and the plurality of ground contacts being clustered about a periphery of the array of electrical contacts.

10. The semiconductor chip of claim 1 incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

11. A semiconductor chip comprising:

first means for providing electrical contact external to the semiconductor chip

second means for providing electrical contact external to the semiconductor chip;

first means for coupling to a first circuit in the semiconductor chip, the first circuit coupling means in communication with the first electrical contact means; and

second means for coupling to a second circuit in the semiconductor chip, the second circuit coupling means in communication with the second electrical contact means;

in which a number of first circuit coupling means is different than a number of second circuit coupling means.

12. The semiconductor chip of claim 11 in which the first and second electrical contact means comprise solder balls in a ball grid array.

13. The semiconductor chip of claim 11 in which the first and second circuit coupling means comprise Through Silicon Vias (TSVs).

14. The semiconductor chip of claim 11 in which the first electrical contact means comprise a power contact, and in which the second electrical contact means comprise a signal contact.

15. The semiconductor chip of claim 14 in which in which the number of first circuit coupling means is larger than the number of second circuit coupling means.

16. The semiconductor chip of claim 11 in which the semiconductor chip is included in a chip package with a memory chip, in which the first and second electrical contact means provide electrical communication with a plurality of contacts on the memory chip.

17. The semiconductor chip of claim 11 incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

18. A method of manufacturing a semiconductor chip, the manufacturing method comprising:

fabricating a plurality of vias coupled to least one circuit in the semiconductor chip; and

fabricating an array of electrical contacts in communication with the plurality of vias, in which a first one of the electrical contacts of the array of electrical contacts is coupled to N vias of the plurality of vias, and in which a second one of the electrical contacts of the array of electrical contacts is coupled to M vias of the plurality of vias, where M and M are positive integers of different values.

19. The method of claim 18 further comprising:

stacking the semiconductor chip with another semiconductor chip in a chip package.

20. The method of claim 18 further comprising:

incorporating the semiconductor chip into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.

21. A method of manufacturing a semiconductor chip, the manufacturing method comprising the steps of:

fabricating a plurality of vias coupled to least one circuit in the semiconductor chip; and

fabricating an array of electrical contacts in communication with the plurality of vias, in which a first one of the electrical contacts of the array of electrical contacts is coupled to N vias of the plurality of vias, and in which a second one of the electrical contacts of the array of electrical contacts is coupled to M vias of the plurality of vias, where M and M are positive integers of different values.

22. The method of claim 21 in which the array of electrical contacts comprises solder bumps.

23. The method of claim 21 further comprising:

stacking the semiconductor chip with another semiconductor chip in a chip package.

24. The method of claim 21 further comprising:

incorporating the semiconductor chip into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer.