STACKED SEMICONDUCTOR PACKAGE

• US 20110193213A1
• Filed: 12/29/2010
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: KIM, Ki Young, NAM, Jong Hyun, BAE, Jin Ho
• Granted Patent: US 8,791,558 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/17104 relative to the bonding areas, e.g. bond pads
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.

Claims

1. A stacked semiconductor package comprising:

a semiconductor chip module comprising at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips stacked on the sub substrate; and

a main substrate supporting the semiconductor chip module.

2. The stacked semiconductor package according to claim 1, wherein the first semiconductor chip and the at least two semiconductor chips are electrically coupled to the sub substrate, and the main substrate is electrically coupled to the at least two sub semiconductor chip modules.

3. The stacked semiconductor package according to claim 1, wherein the sub substrate has a first surface with first sub connection pads and a second surface facing away from the first surface, each of the second semiconductor chips have second bonding pads connected with the first sub connection pads, and the main substrate comprises main connection pads connected with the respective first sub connection pads.

4. The stacked semiconductor package according to claim 3, wherein the sub substrate comprises:

a support layer attached to a second surface of the first semiconductor chip and first bonding pads disposed on a first surface of the first semiconductor chip;

bumps formed over the first bonding pads and connecting the first bonding pads with the first sub connection pads;

an insulation layer covering an upper surface of the support layer including the first semiconductor chip, exposing upper ends of the bumps, and supporting the first sub connection pads; and

a solder resist formed over the insulation layer to expose the first sub connection pads.

5. The stacked semiconductor package according to claim 3, wherein the second semiconductor chips are stacked to be offset from one another such that the respective second bonding pads are exposed.

6. The stacked semiconductor package according to claim 3, wherein the first sub connection pads and the respective second bonding pads are connected with each other by the medium of bonding wires.

7. The stacked semiconductor package according to claim 3, wherein the first sub connection pads and the main connection pads are connected with each other by the medium of bonding wires.

8. The stacked semiconductor package according to claim 3, further comprising:

a controller chip attached onto the semiconductor chip module and having third bonding pads which are connected with the first sub connection pads of any one sub semiconductor chip module among the sub semiconductor chip modules constituting the semiconductor chip module.

9. The stacked semiconductor package according to claim 8, wherein the third bonding pads and the first sub connection pads are connected with each other by the medium of bonding wires.

10. The stacked semiconductor package according to claim 3, wherein the sub substrate included in at least one sub semiconductor chip module among the sub semiconductor chip modules comprises:

second sub connection pads formed over the first surface and connected with the main connection pads; and

a controller chip embedded along with the first semiconductor chip on a side of the first semiconductor chip and having third bonding pads which are connected with the second sub connection pads.

11. The stacked semiconductor package according to claim 10, wherein the sub substrate including the controller chip comprises:

first bonding pads disposed over a first surface of the first semiconductor chip;

a support layer attached to a second surface of the first semiconductor chip facing away from a first surface of the first semiconductor chip;

first bumps formed over the first bonding pads and connecting the first bonding pads with the first sub connection pads;

second bumps formed over the third bonding pads and connecting the third bonding pads with the second sub connection pads;

an insulation layer covering an upper surface of the support layer including the first semiconductor chip and the controller chip, exposing upper ends of the first and second bumps, and supporting the first and second sub connection pads; and

a solder resist formed over the insulation layer to expose the first and second sub connection pads.

12. The stacked semiconductor package according to claim 10, wherein the main connection pads and the second sub connection pads are connected with each other by the medium of bonding wires.

13. The stacked semiconductor package according to claim 10, wherein the second sub connection pads and the third bonding pads are connected with each other by the medium of bonding wires.

14. A stacked semiconductor package comprising:

a main substrate having an upper surface over which main connection pads are formed and a lower surface which faces away from the upper surface;

at least two first semiconductor chips stacked over the upper surface and having first bonding pads which are connected with the main connection pads; and

at least one sub semiconductor chip module stacked over the first semiconductor chips,

the sub semiconductor chip module having a sub substrate which has a first surface with sub connection pads formed thereon and connected with the main connection pads and a second surface facing away from the first surface and in which a second semiconductor chip with second bonding pads connected with the sub connection pads is embedded and at least two third semiconductor chips which are stacked over the first surface and have third bonding pads connected with the sub connection pads.

15. The stacked semiconductor package according to claim 14, wherein the sub substrate comprises:

a support layer attached to the other surface of the second semiconductor chip facing away from one surface of the second semiconductor chip over which the second bonding pads are disposed;

bumps formed over the second bonding pads and connecting the second bonding pads with the sub connection pads;

an insulation layer covering an upper surface of the support layer including the second semiconductor chip, exposing upper ends of the bumps, and supporting the sub connection pads; and

a solder resist formed over the insulation layer to expose the sub connection pads.

16. The stacked semiconductor package according to claim 14, wherein the first semiconductor chips are stacked to deviate from one another such that the first bonding pads are exposed.

17. The stacked semiconductor package according to claim 14, wherein the main connection pads and the first bonding pads are connected with each other by the medium of bonding wires.

18. The stacked semiconductor package according to claim 14, wherein the sub connection pads and the main connection pads are connected with each other by the medium of bonding wires.

19. The stacked semiconductor package according to claim 14, wherein the third semiconductor chips are stacked to deviate from one another such that the third bonding pads are exposed.

20. The stacked semiconductor package according to claim 14, wherein the sub connection pads and the respective third bonding pads are connected with each other by the medium of bonding wires.