SEMICONDUCTOR PACKAGE

• US 20110193215A1
• Filed: 02/09/2011
• Published: 08/11/2011
• Est. Priority Date: 02/09/2010
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: UEMATSU, Yutaka, TOYAMA, Masahiro, OSAKA, Hideki
• Application Number:
  US13/023,565
• Publication Number:
  US 20110193215A1
• Time in Patent Office: Days
• US Class Current: 257/691
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06153 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

Means for decreasing parasitic inductance by a realistic mounting method is provided. On a surface layer of a semiconductor package, there is provided a ground pad having a plurality of comb-tooth-shaped ground pads which are connecting points for wire bonding and are protruded on the surface layer of the semiconductor package. A power-supply pad is arranged between the comb-tooth-shaped ground pads. Two long and short ground wires are arranged in one comb-tooth-shaped ground pad. Also, two long and short power-supply wires are arranged in one power-supply pad. By arranging the long ground wire and the long power-supply wire so as to be parallel and close to each other and arranging the short power-supply wire and the short ground wire so as to be parallel and close to each other, the parasitic inductance is decreased.

Claims

1. A semiconductor package mounting a semiconductor chip and having connection with the semiconductor chip by wire bonding, wherein

the semiconductor package has a ground pad, which is a connecting point for the wire bonding, on a surface layer of the semiconductor package,

the ground pad has a comb-tooth-shaped ground pad protruding on the surface layer of the semiconductor package, and

two or more ground wires are connected to the comb-tooth-shaped ground pad.

2. The semiconductor package according to claim 1, wherein

the semiconductor package further has a power-supply pad to which two or more power-supply wires are connected, and

one ground wire of the two or more ground wires and one power-supply wire of the two or more power-supply wires are substantially parallel to each other and have substantially the same length to be a pair.

3. The semiconductor package according to claim 2, wherein

two or more comb-tooth-shaped ground pads are provided, and

the power-supply pad is arranged on the surface layer of the semiconductor package so as to be sandwiched by two comb-tooth-shaped ground pads.

4. The semiconductor package according to claim 1, wherein

a difference between lengths of the two or more ground wires connected to the comb-tooth-shaped ground pad is equal to or larger than a distance between wire pads on the semiconductor chip side.

5. The semiconductor package according to claim 4, wherein

a part of the comb-tooth-shaped ground pad has a length which is twice a portion parallel to the power-supply pad or larger,

a ground wire having a length different from that of the ground wire is connected from the semiconductor chip to a tip side of the comb-tooth-shaped ground pad having the length which is twice or larger, and

a signal wire is arranged so as to be parallel to the ground wire connected to the tip side of the comb-tooth-shaped ground pad having the length which is twice or larger.

6. The semiconductor package according to claim 5, wherein

the semiconductor package further has an I/O power-supply pad on the surface layer of the semiconductor package, and

an I/O power-supply wire is connected to the I/O power-supply pad so as to be parallel to the signal wire.

7. The semiconductor package according to claim 6, wherein

the semiconductor package has:

a power-supply via hole so as to be in contact with an outer peripheral side of the semiconductor package of the power-supply pad;

an I/O power-supply via hole so as to be in contact with the semiconductor chip side of the I/O power-supply pad; and

a ground via hole in the comb-tooth-shaped ground pad in the vicinity of the power-supply via hole or the I/O power-supply via hole.

8. The semiconductor package according to claim 7, wherein

a long wire and a short wire are alternately arranged to each other as the I/O power-supply wire and the ground wire being parallel to the I/O power-supply wire and having the same length as that of the I/O power-supply wire, and

a long wire and a short wire are alternately arranged to each other as the signal wire and the ground wire being parallel to the signal wire and the I/O power-supply wire and having the same length as those of the signal wire and the I/O power-supply wire.

9. A semiconductor package mounting a semiconductor chip and having connection with the semiconductor chip by wire bonding, wherein

the semiconductor package has a ground pad and a power-supply pad, which are connecting points for the wire bonding, on a surface layer of the semiconductor package,

the ground pad has a comb-tooth-shaped ground pad protruding on the surface layer of the semiconductor package,

the power-supply pad has a comb-tooth-shaped power-supply pad protruding on the surface layer of the semiconductor package, and

the comb-tooth-shaped ground pad and the comb-tooth-shaped power-supply pad are adjacent to each other in a peripheral direction of the semiconductor package.

10. The semiconductor package according to claim 9, wherein

the ground pad is arranged in an inner peripheral side of the semiconductor package, and the power-supply pad is arranged in an outer peripheral side of the semiconductor package.

11. The semiconductor package according to claim 10, wherein

two wires having different lengths from each other are arranged in each of the comb-tooth-shaped ground pad and the comb-tooth-shaped power-supply pad, and

a long wire and a short wire are alternately arranged to each other as each of the two wires arranged in the comb-tooth-shaped ground pad and the two wires arranged in the comb-tooth-shaped power-supply pad.

12. The semiconductor package according to claim 11, wherein

the comb-tooth-shaped ground pad and the comb-tooth-shaped power-supply pad are shaped in a substantially parallelogram oblique to a tip of the chip.

13. The semiconductor package according to claim 10, wherein

total four wires having two types of lengths are arranged in the comb-tooth-shaped ground pad, and

a via hole for ground connection is arranged between connecting points for the long wire and the short wire arranged in the comb-tooth-shaped ground pad.

14. The semiconductor package according to claim 13, wherein

the comb-tooth-shaped ground pad is shaped in a parallelogram oblique to a tip of the chip, and each connecting position for the four wires connected to the same comb-tooth-shaped ground pad is arranged so as to have the same distance from a center line of the comb-tooth-shaped ground pad.

15. The semiconductor package according to claim 13, wherein

the comb-tooth-shaped ground pad is shaped in a trapezoid oblique to the tip of the chip, and each connecting position for the four wires connected to the same comb-tooth-shaped ground pad is arranged so as to have the same distance from a center line of the comb-tooth-shaped ground pad.

16. The semiconductor package according to claim 10, wherein

total four wires having two types of lengths are arranged in the comb-tooth-shaped power-supply pad, and

a via hole for power-supply connection is arranged between connecting points for the long wire and the short wire arranged in the comb-tooth-shaped power-supply pad.

17. The semiconductor package according to claim 16, wherein

the comb-tooth-shaped power-supply pad is shaped in a parallelogram oblique to a tip of the chip, and each connecting position for the four wires connected to the same comb-tooth-shaped power-supply pad is arranged so as to have the same distance from a center line of the comb-tooth-shaped power-supply pad.

18. The semiconductor package according to claim 16, wherein

the comb-tooth-shaped power-supply pad is shaped in a trapezoid oblique to a tip of the chip, and each connecting position for the four wires connected to the same comb-tooth-shaped power-supply pad is arranged so as to have the same distance from a center line of the comb-tooth-shaped power-supply pad.

19. The semiconductor package according to claim 18, wherein

the semiconductor package has a wiring connected to a wire pad on the surface layer of the semiconductor chip, and

power supply and ground are alternately arranged to each other at a connecting portion with wiring in the semiconductor chip.