3DIC Architecture with Interposer for Bonding Dies

• US 20110193221A1
• Filed: 05/05/2010
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Yung-Chi, Yu, Chen-Hua, Lin, Jing-Cheng, Chen, Ming-Fa, Hu, Hsien-Pin, Lai, Jiun Ren
• Granted Patent: US 10,297,550 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/07 Structure, shape, material or disposition of the bonding areas after the connecting process
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Claims

1. A device comprising:

an interposer substantially free from integrated circuit devices, wherein the interposer comprises;

a substrate having a first side and a second side opposite to the first side;

a plurality of through-substrate vias (TSVs) in the substrate;

a first interconnect structure overlying the first side of the substrate and electrically coupled to at least one of the plurality of TSVs; and

a second interconnect structure overlying the second side of the substrate and electrically coupled to at least one of the plurality of TSVs;

a first die bonded onto the first interconnect structure; and

a second die bonded onto the second interconnect structure.

2. The device of claim 1 further comprising:

an encapsulating material overlying the second interconnect structure and encircling the second die;

a conductive via penetrating the encapsulating material and electrically coupled to the second interconnect structure;

a third interconnect structure overlying the encapsulating material and electrically coupled to the conductive via; and

a bump formed overlying the third interconnect structure and electrically coupled to the conductive via.

3. The device of claim 2, wherein the encapsulating material comprises a molding compound.

4. The device of claim 1 further comprising:

an encapsulating material overlying the second die; and

a cavity between the encapsulating material and the second die.

5. The device of claim 4 further comprising:

a conductive via penetrating the encapsulating material and electrically coupled to the second interconnect structure;

a third interconnect structure overlying the encapsulating material and electrically coupled to the conductive via; and

a bump formed overlying the third interconnect structure and electrically coupled to the conductive via.

6. The device of claim 5, wherein the encapsulating material comprises a dummy silicon substrate.

7. The device of claim 1, wherein the plurality of TSVs have different lengths, and extending from the substrate into different depths of the first interconnect structure.

8. The device of claim 1 further comprising a solder bump on the second interconnect structure adjacent to the second die.

9. A device comprising:

an interposer substantially free from integrated circuit devices, wherein the interposer comprises;

a substrate having a first side and a second side opposite to the first side;

a plurality of through-substrate vias (TSVs) in the substrate;

a first interconnect structure overlying the first side of the substrate and electrically coupled to at least one of the plurality of TSVs; and

an opening in the substrate adjacent to at least one of the plurality of TSVs;

a first die bonded onto the first interconnect structure; and

a second die formed in the opening and bonded onto the first interconnect structure.

10. The device of claim 9 further comprising a second interconnect structure overlying the second side of the substrate and electrically coupled to at least one of the plurality of TSVs.

11. The device of claim 10, wherein the second die is electrically coupled to the second interconnect structure through the first interconnect structure.

12. The device of claim 10 further comprising a plurality of solder bumps overlying the second interconnect structure and electrically coupled to the plurality of TSVs.

13. The device of claim 9 further comprising an underfill material filling the opening.

14. A method of forming a device comprising:

providing a silicon substrate substantially free from integrated circuit devices;

forming a through-substrate via (TSV) penetrating from the front side of the silicon substrate and reaching a predetermined depth of the silicon substrate;

forming a first interconnect structure over the front side of the silicon substrate, wherein the first interconnect structure comprises at least one dielectric layer and metal features in the at least one dielectric layer;

bonding a first die onto the first interconnect structure;

removing the backside of the silicon substrate to expose an end of the TSV;

forming a second interconnect structure on the backside of the silicon substrate and electrically coupled to the exposed end of the TSV;

forming an opening penetrating the second interconnect structure and the silicon substrate to reach a surface of the first interconnect structure; and

bonding a second die onto the surface of the first interconnect structure in the opening.

15. The method of claim 14 further comprising forming a plurality of solder bumps on the second interconnect structure.

16. The method of claim 14 further comprising forming an underfill material in the opening.