ESD Protection Integrated at System Level

• US 20110194220A1
• Filed: 02/02/2011
• Published: 08/11/2011
• Est. Priority Date: 02/02/2010
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: MARUM, Steve E., DUVVURY, Charvaka
• Application Number:
  US13/019,845
• Publication Number:
  US 20110194220A1
• Time in Patent Office: Days
• US Class Current: 361/58
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing

Abstract

An electronic system including an assembly with a protection clamp for discharging a portion of the incoming pulse, the un-discharged residual pulse (132) including a spike voltage (150, 202) for a first time duration (151, 203) followed by a bulk voltage (160, 302) smaller than the spike voltage for a second time duration (161, 303) greater than the first time duration; an integrated circuit device coupled with the board, the device allowing a peak current (211) at the insulator breakdown voltage (213), and including a pin protection clamp allowing a threshold current (311) at a threshold voltage (313) during the second time duration; and an isolation impedance integrated with the system for weakening the residual pulse, the impedance being the greater of a first resistor (220), determined by dividing the voltage difference between spike and insulator breakdown voltage through the peak current, and a second resistor (320), determined by dividing the voltage difference between the bulk and threshold voltage through the threshold current.

Claims

1. An electronic system protected against an incoming energy pulse, comprising:

an assembly including a protection clamp for discharging a portion of the incoming pulse, the un-discharged residual pulse including a spike voltage for a first time duration followed by a bulk voltage smaller than the spike voltage for a second time duration greater than the first time duration;

an integrated circuit device tied to the assembly, the device allowing a peak current at the insulator breakdown voltage, and including a pin protection clamp allowing a threshold current at a threshold voltage during the second time duration; and

an isolation impedance, integrated with the assembly and device, for weakening the residual pulse, the impedance being the greater of a first resistor, determined by dividing the voltage difference between spike and insulator breakdown voltage through the peak current, and a second resistor, determined by dividing the voltage difference between the bulk and threshold voltage through the threshold current.

2. The system of claim 1 wherein the isolation impedance is integrated in an assembly trace connecting to the device pin.

3. The system of claim 1 wherein the isolation impedance is integrated inside the device package in a connection from a package terminal to a chip terminal.

4. The system of claim 1 wherein the isolation impedance is integrated on the circuitry of the device chip in a conductive line from a chip terminal to the internal protection clamp.

5. A method for fabricating an electronic system protected against an incoming energy pulse, comprising the steps of:

providing an assembly including an external protection clamp for discharging a first portion of the incoming pulse, leaving un-discharged a residual pulse having a voltage/time characteristic;

analyzing the voltage/time characteristic for identifying a first regime having a spike voltage for a first time duration followed by a second regime having a bulk voltage smaller than the spike voltage for a second time duration greater than the first duration;

coupling an integrated circuit device to the assembly, the device allowing a peak current at the insulator breakdown voltage, and further including a pin with an internal protection clamp having a current/voltage failure characteristic for the second time duration allowing a threshold current at a threshold voltage; and

integrating into the system of assembly and device the greater isolation impedance between

a first resistor being equal to or greater than the voltage difference between spike and oxide breakdown voltage divided by the peak current; and

a second resistor being equal to or greater than the voltage difference between the bulk and threshold voltage divided by the threshold current.

6. The method of claim 5 wherein the greater isolation impedance is integrated in an assembly trace connecting to the device pin.

7. The method of claim 5 wherein the greater isolation impedance is integrated inside the device package in a connection from a package terminal to a chip terminal.

8. The method of claim 5 wherein the greater isolation impedance is integrated in the circuitry of the device chip in a conductive line from a chip terminal to the internal protection clamp.

9. An integrated circuit device, comprising:

an I/O pin;

an internal protection clamp; and

an isolation impedance element connected between the internal protection clamp and the pin, wherein the isolation impedance element has a resistance in the range of 5Ω

to 100Ω

.

10. The device of claim 9, wherein the isolation impedance element is selected to protect the internal protection clamp from an expected residual pulse from a theoretical external protection clamp such that the resistance between the internal protection clamp and the theoretical external protection clamp is:

not less than a voltage difference between an expected spike voltage and an oxide breakdown voltage of the internal protection clamp divided by an allowed peak current; and

not less than a voltage difference between an expected bulk voltage and a threshold voltage of the internal protection clamp divided by an allowed threshold current.

11. The device of claim 9, wherein the isolation impedance element is a discrete resistor part.

12. The device of claim 9, wherein the isolation impedance element comprises a resistor material having a higher resistance than a resistance of a metal connected between the internal clamp and the pin.

13. The device of claim 9, wherein the isolation impedance element comprises a portion of a metal connected between the internal protection clamp and pin having an additional length.

14. The device of claim 9, wherein the isolation impedance element comprises a narrowed portion of a metal connected between the internal protection clamp and a pin.

15. The device of claim 9, wherein the resistance is between 10Ω

and 50Ω

.