SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE

• US 20110194331A1
• Filed: 02/02/2011
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Uochi, Hideki, Kawae, Daisuke
• Granted Patent: US 8,514,609 B2
• Time in Patent Office: Days
• US Class Current: 365/149
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source and drain electrodes of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a signal line connected to a capacitor as a reading signal line or a signal line connected to one of a source and drain electrodes of the reading transistor as a reading signal line so that a reading potential is supplied to the reading signal line, and then detecting a potential of the bit line.

Claims

1. A semiconductor device comprising memory cells,

the memory cells each comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring;

a second wiring; and

a third wiring,

wherein one of a source electrode and a drain electrode of the second transistor and a gate electrode of the first transistor are electrically connected to one electrode of the capacitor,

wherein the other electrode of the capacitor is electrically connected to the first wiring,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring of a different memory cell,

wherein the other of the source electrode and the drain electrode of the second transistor and the other of the source electrode and the drain electrode of the first transistor are electrically connected to the second wiring, and

wherein a gate electrode of the second transistor is electrically connected to the third wiring.

2. The semiconductor device according to claim 1, wherein the second transistor comprises an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

4. The semiconductor device according to claim 1, wherein a switching rate of the first transistor is higher than a switching rate of the second transistor.

5. A method of driving a semiconductor device comprising a memory cell,

the memory cell comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring; and

a second wiring,

wherein the second transistor is connected between the second wiring and a gate electrode of the first transistor, and

wherein one electrode of the capacitor of is connected to the gate electrode of the first transistor and the other electrode of the capacitor is connected to the first wiring,

the method comprising the steps of;

turning on the second transistor when the first wiring is supplied with a low-level potential and the first transistor is in an off-state,

supplying a high-level potential or a low-level potential supplied to the second wiring to the gate electrode of the first transistor when the first wiring is supplied with a low-level potential and the first transistor is in an off-state, and

turning off the second transistor after the step of turning on the second transistor and the step of supplying the high-level potential or the low-level potential to the gate electrode of the first transistor so that a potential of the gate electrode of the first transistor is held.

6. The method of driving the semiconductor device according to claim 5, wherein a difference between the high-level potential and the low-level potential supplied to the second wiring is lower than a threshold voltage of the first transistor.

7. A method of driving a semiconductor device comprising memory cells,

the memory cells each comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring; and

a second wiring,

wherein the first transistor is connected between the first wiring of a different memory cell and the second wiring,

wherein the second transistor is connected between the second wiring and a gate electrode of the first transistor, and

wherein one electrode of the capacitor is connected to the gate electrode of the first transistor and the other electrode of the capacitor is connected to the first wiring,

the method comprising the steps of;

supplying a first potential to the first wiring of the different memory cell and supplying a second potential to the second wiring when the second transistor is in an off-state, and

supplying a third potential of the first wiring which is connected to the other electrode of the capacitor to the gate electrode of the first transistor via the capacitor after the step of supplying the second potential to the second wiring, so that on or off of the first transistor is detected.

8. The method of driving the semiconductor device according to claim 7, wherein the first potential is different from the second potential.

9. A semiconductor device comprising memory cells,

the memory cells each comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring;

a second wiring; and

a third wiring,

wherein one of a source electrode and a drain electrode of the second transistor and a gate electrode of the first transistor are electrically connected to one electrode of the capacitor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the first wiring,

wherein the other of the source electrode and the drain electrode of the second transistor and the other of the source electrode and the drain electrode of the first transistor are electrically connected to the second wiring,

wherein a gate electrode of the second transistor is electrically connected to the third wiring, and

wherein the other electrode of the capacitor is electrically connected to the first wiring of a different memory cell.

10. The semiconductor device according to claim 9, wherein the second transistor comprises an oxide semiconductor.

11. The semiconductor device according to claim 9, wherein an off-state current of the second transistor is lower than an off-state current of the first transistor.

12. The semiconductor device according to claim 9, wherein a switching rate of the first transistor is higher than a switching rate of the second transistor.

13. A method of driving a semiconductor device comprising a memory cell,

the memory cell comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring; and

a second wiring,

wherein the first transistor is connected between the first wiring and the second wiring,

wherein the second transistor is connected between the second wiring and a gate electrode of the first transistor, and

wherein one electrode of the capacitor is connected to the gate electrode of the first transistor,

the method comprising the steps of;

turning on the second transistor when the first transistor is in an off-state,

supplying a high-level potential or a low-level potential supplied to the second wiring to the gate electrode of the first transistor when the first transistor is in an off-state, and

turning off the second transistor after the step of turning on the second transistor and the step of supplying the high-level potential or the low-level potential to the gate electrode of the first transistor, so that a potential of the gate electrode of the first transistor is held.

14. The method of driving the semiconductor device according to claim 13, wherein a difference between the high-level potential and the low-level potential supplied to the second wiring is lower than a threshold voltage of the first transistor.

15. A method of driving a semiconductor device comprising a memory cell,

the memory cell comprising:

a first transistor;

a second transistor;

a capacitor;

a first wiring; and

a second wiring,

wherein the first transistor is connected between the first wiring and the second wiring,

wherein the second transistor is connected between the second wiring and a gate electrode of the first transistor, and

wherein one electrode of the capacitor is connected to the gate electrode of the first transistor,

the method comprising the steps of;

supplying a second potential to the second wiring when the second transistor is in an off-state, and

supplying a first potential to the first wiring after the step of supplying the second potential to the second wiring, so that on or off of the first transistor is detected.

16. The method of driving the semiconductor device according to claim 15, wherein the first potential is different from the second potential.