WORD-LINE DRIVER USING LEVEL SHIFTER AT LOCAL CONTROL CIRCUIT

• US 20110194362A1
• Filed: 02/09/2010
• Published: 08/11/2011
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: LIAO, Hung-Jen, HUNG, Lee-Cheng, CHENG, Hong-Chen, CHANDRA, Uppu Sharath, Wu, Chung-Yi, CHEN, Hsu-Shun, LU, Chung-Ji
• Granted Patent: US 8,427,888 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A representative circuit device includes a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.

Claims

1. A circuit device comprising:

a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal; and

a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to the local control circuit to receive the level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array.

2. The circuit device of claim 1, wherein the word-line driver is a two-gate delay word-line driver.

3. The circuit device of claim 2, wherein the two-gate delay word-line driver includes a first gate having a first transistor to receive the level shifted first address signal from the level shifter and a second transistor to receive the first address signal, which reduces gate delay from the level shifter, wherein the first gate outputs a low signal responsive to receiving a high signal from the first address signal.

4. The circuit device of claim 3, wherein the two-gate delay word-line driver further includes a second gate having an inverter to receive the output of the first gate, wherein the output of the second gate is electrically coupled to the word line of the memory cell array.

5. The circuit device of claim 1, wherein the word-line driver is a four-gate delay word-line driver.

6. The circuit device of claim 5, wherein the four-gate delay word-line driver includes a decoder stage that includes a first gate and second gate to receive second and third address signals of the plurality of address signals.

7. The circuit device of claim 6, wherein the four-gate delay word-line driver further includes a third gate having a first transistor and a first inverter to receive the level shifted first address signal, which reduces gate delay from the level shifter, wherein the third gate outputs a low signal responsive to receiving a high signal from the first address signal.

8. The circuit device of claim 7, wherein the four-gate delay word-line driver further includes a fourth gate having an inverter to receive the output of the third gate, wherein the output of the fourth gate is electrically coupled to the word line of the memory cell array.

9. The circuit device of claim 1, wherein the word-line driver further has second and third inputs to receive second and third address signals of the plurality of address signals.

10. A memory circuit comprising:

a local control circuit having a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from a first voltage level to a second voltage level, providing a level shifted first address signal;

a word-line driver having at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input to receive the level shifted address signal from the level shifter; and

a memory cell array having a word line that is coupled to an output of the word-line driver.

11. The memory circuit of claim 10, wherein the word-line driver is a two-gate delay word-line driver.

12. The memory circuit of claim 11, wherein the two-gate delay word-line driver includes a first gate having a first transistor to receive the level shifted first address signal from the level shifter and a second transistor to receive the first address signal, which reduces gate delay from the level shifter, wherein the first gate outputs a low signal responsive to receiving a high signal from the first address signal.

13. The memory circuit of claim 12, wherein the two-gate delay word-line driver includes a second gate having an inverter to receive the output of the first gate, wherein the output of the second gate is electrically coupled to the word line of the memory cell array.

14. The memory circuit of claim 10, wherein the word-line driver is a four-gate delay word-line driver.

15. The memory circuit of claim 14, wherein the four-gate delay word-line driver includes a decoder stage that includes a first gate and second gate to receive second and third address signals of the plurality of address signals.

16. The memory circuit of claim 15, wherein the four-gate delay word-line driver further includes a third gate having a first transistor to receive the first address signal from the level shifter and a first inverter to receive the first address signal, which reduces gate delay from the level shifter, wherein the third gate outputs a low signal responsive to receiving a high signal from the first address signal.

17. The memory circuit of claim 16, wherein the four-gate delay word-line driver further includes a fourth gate having an inverter to receive the output of the third gate, wherein the output of the fourth gate is electrically coupled to the word line of the memory cell array.

18. The memory circuit of claim 10, wherein the word-line driver further has second and third inputs to receive second and third address signals of the plurality of address signals.

19. A word-line driver comprising:

at least one input for receiving a plurality of address signals, wherein the at least one input includes a first input that is coupled to a local control circuit to receive a level shifted first address signal, and an output that is electrically coupled to a word line of a memory cell array, wherein the local control circuit includes a level shifter, wherein in response to receipt of a first address signal the level shifter shifts the first address signal from the first voltage level to a second voltage level, providing the level shifted first address signal.

20. The word-line driver of claim 19, wherein the word-line driver is a two-gate delay word-line driver or a four-gate delay word-line driver.