NOVEL HARD MASK REMOVAL METHOD

• US 20110195575A1
• Filed: 02/11/2010
• Published: 08/11/2011
• Est. Priority Date: 02/11/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: WANG, Shiang-Bau
• Granted Patent: US 8,361,338 B2
• Time in Patent Office: Days
• US Class Current: 438/692
• CPC Class Codes: H01L 21/02071 the processing being a delineation, e.g. RIE, of conductive layers
• CPC Class Codes: H01L 21/02107 Forming insulating materials on a substrate
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32139 using masks

Abstract

The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.

Claims

1. A method of removing a hard mask used for patterning gate stacks, comprising:

patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask is deposited over the polysilicon layer to assist its patterning;

depositing a dielectric layer on the substrate after the gate stacks are patterned;

planarizing a first portion of the dielectric layer by chemical mechanical polish (CMP) to remove topography on the substrate;

removing a second portion of the dielectric layer and the hard mask by using an etching gas; and

etching the remaining dielectric layer by using a wet etching chemistry.

2. The method of claim 1, wherein a first etching ratio of the dielectric layer to the hard mask by the etching gas is between about 0.5 to about 2.

3. The method of claim 1, wherein a second etching ratio of the dielectric layer to other films on the substrate by the wet etching chemistry is greater than about 4.

4. The method of claim 1, further comprising:

densifying the dielectric layer after the dielectric layer is deposited and before the first portion of the dielectric layer is planarized to increase hardness of the dielectric film and to enable the dielectric layer to be planarized by CMP.

5. The method of claim 4, wherein the dielectric film is densified by annealing at a temperature less than about 450°

C.

6. The method of claim 5, wherein the annealing utilizes rapid thermal annealing or laser annealing for a duration less than 10 minutes.

7. The method of claim 1, wherein the etching gas is activated by a remote plasma.

8. The method of claim 1, wherein the etching gas forms an etch byproduct that deposit on the substrate surface with the dielectric layer, and wherein the etch byproduct deposited on the substrate surface is removed by heating.

9. The method of claim 8, wherein the substrate is repeatedly exposed to the etching gas to form a layer of the etch byproduct and then be heated to evaporate the etch byproduct until the second portion of the dielectric layer is removed.

10. The method of claim 1, wherein the etching gas include a mixture of HF and NH₃, or a mixture of plasmarized NF₃ and NH₃.

11. The method of claim 8, wherein the heating temperature is between about 125°

C. to about 180°

C.

12. The method of claim 1, wherein the wet etching chemistry is a diluted HF solution.

13. The method of claim 1, wherein the hard mask is made of an oxide layer or an oxide layer over a nitride layer.

14. The method of claim 1, wherein the dielectric layer is a spin-on-glass, a spin-on-dielectric, a TEOS/Ozone oxide, or a flowable CVD oxide film.

15. A method of removing a hard mask used for patterning gate stacks, comprising:

patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the hard mask is deposited over the polysilicon layer to assist its patterning;

depositing a dielectric layer on the substrate after the gate stacks are patterned;

planarizing a first portion of the dielectric layer by chemical mechanical polish (CMP) to remove topography on the substrate, wherein a first etching ratio of the dielectric layer to the hard mask by the etching gas is between about 0.5 to about 2;

removing a second portion of the dielectric layer and the hard mask by using an etching gas; and

etching the remaining dielectric layer by using a wet etching chemistry, wherein a second etching ratio of the dielectric layer to other films on the substrate by the wet etching chemistry is greater than about 4.

16. The method of claim 15, further comprising:

densifying the dielectric layer after the dielectric layer is deposited and before the first portion of the dielectric layer is planarized to increase hardness of the dielectric film and to enable the dielectric layer to be planarized by CMP, wherein the dielectric film is densified by annealing at a temperature less than about 450°

C.

17. The method of claim 15, wherein the etching gas forms an etch byproduct that deposit on the substrate surface with the dielectric layer, and wherein the etch byproduct deposited on the substrate surface is sublimed by heating, and wherein the substrate is repeatedly exposed to the etching gas to form a layer of the etch byproduct and then be heated to sublime the etch byproduct until the second portion of the dielectric layer is removed.

18. The method of claim 15, wherein the dielectric layer is a spin-on-glass, a spin-on-dielectric, a TEOS/Ozone oxide, or a flowable CVD oxide film.

19. The method of claim 15, wherein the etching gas include a mixture of HF and NH₃, or a mixture of plasmarized NF₃ and NH₃.

20. A method of removing a dual-layer hard mask used for patterning gate stacks, comprising:

patterning gate stacks on a substrate, wherein the gate stacks include a polysilicon layer and the dual-layer hard mask is deposited over the polysilicon layer to assist its patterning, wherein the dual-layer hard mask includes an oxide layer over a nitride layer;

depositing a dielectric layer on the substrate after the gate stacks are patterned;

planarizing a first portion of the dielectric layer by chemical mechanical polish (CMP) to remove topography on the substrate, wherein a first etching ratio of the dielectric layer to the dual-layer hard mask by the etching gas is between about 0.5 to about 2;

removing a second portion of the dielectric layer and the dual-layer hard mask by a first etching gas and a second etching gas, wherein the first etching gas removes the second portion of the dielectric layer and the oxide layer of the dual-layer hard mask, and wherein the second etching gas removes the nitride layer of the dual-layer hard mask; and

etching the remaining dielectric layer by using a wet etching chemistry, wherein a second etching ratio of the dielectric layer to other films on the substrate by the wet etching chemistry is greater than about 4.