MEMORY MANAGEMENT AND WRITING METHOD AND REWRITABLE NON-VOLATILE MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME

• US 20110197014A1
• Filed: 03/29/2010
• Published: 08/11/2011
• Est. Priority Date: 02/05/2010
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang
• Granted Patent: US 8,296,507 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A memory management and writing method for managing a plurality of physical units of a memory chip is provided. The present method includes grouping the physical units into a first physical unit group and a second physical unit group, recording and calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group, and calculating an erase count difference between the first erase count and the second erase count. The present method also includes determining whether the erase count difference is larger than an erase count difference threshold when a write command is received. The method further includes executing a switched writing procedure to write data corresponding to the write command into the memory chip when the erase count difference is larger than the erase count difference threshold. Thereby, the lifespan of the memory chip is effectively prolonged.

Claims

1. A memory management and writing method, for managing a plurality of physical units of a memory chip, the memory management and writing method comprising:

configuring a plurality of logical units;

grouping the physical units into a first physical unit group and a second physical unit group;

grouping a portion of the physical units in the first physical unit group into a first data area and a first spare area corresponding to the first data area;

grouping a portion of the physical units in the second physical unit group into a second data area and a second spare area corresponding to the second data area;

mapping the logical units to the physical units in the first data area and the second data area;

recording erase counts corresponding to a plurality of the physical units in the first physical unit group and the second physical unit group;

calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group according to the erase counts, and calculating an erase count difference between the first erase count and the second erase count; and

determining whether the erase count difference is larger than an erase count difference threshold when a write command corresponding to a first logical unit among the logical units and new data corresponding to the write command are received, wherein the first logical unit is mapped to a first physical unit among the physical units in the first data area,

wherein a switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold, and the switched writing procedure comprises;

getting a second physical unit from the physical units in the second spare area; and

writing the new data into the second physical unit.

2. The memory management and writing method according to claim 1, wherein the switched writing procedure further comprises:

associating the second physical unit to the second data area and re-mapping the first logical unit to the second physical unit.

3. The memory management and writing method according to claim 1, wherein a general writing procedure is executed when the erase count difference is not larger than the erase count difference threshold, and the general writing procedure comprises:

getting a third physical unit from the physical units in the first spare area; and

writing the new data into the third physical unit.

4. The memory management and writing method according to claim 3, wherein the general writing procedure further comprises:

moving valid data in the first physical unit to the third physical unit by using a copyback command set, wherein the copyback command set is used for reproducing and writing data in the memory chip.

5. The memory management and writing method according to claim 3, wherein the general writing procedure further comprises:

associating the third physical unit to the first data area, and re-mapping the first logical unit to the third physical unit.

6. The memory management and writing method according to claim 2 further comprising:

calculating a logical unit amount difference, wherein the logical unit amount difference is obtained by deducting the number of the logical units mapped to the physical units in the second data area from the number of the logical units mapped to the physical units in the first data area; and

determining whether the logical unit amount difference is equal to a logical unit amount difference threshold,

wherein a wear levelling procedure is executed when the logical unit amount difference is equal to the logical unit amount difference threshold, and the wear levelling procedure comprises;

getting a fourth physical unit from the physical units in the first spare area;

getting a fifth physical unit from the physical units in the second data area, wherein the fifth physical unit is mapped to a second logical unit among the logical units;

moving valid data in the third logical unit to the fourth physical unit; and

associating the fourth physical unit to the first data area, associating the fifth physical unit to the second spare area, and re-mapping the second logical unit to the fourth physical unit.

7. The memory management and writing method according to claim 1, wherein the physical units in the memory chip respectively belong to a first plane and a second plane,

wherein the step of grouping the physical units into the first physical unit group and the second physical unit group comprises:

grouping the physical units belonging to the first plane into the first physical unit group and the physical units belonging to the second plane into the second physical unit group,

wherein data corresponding to the first plane cannot be copied to the second plane by the copyback command set, and data corresponding to the second plane cannot be copied to the first plane by the copyback command set.

8. The memory management and writing method according to claim 1 further comprising:

calculating a logical unit amount difference, wherein the logical unit amount difference is obtained by deducting the number of the logical units mapped to the physical units in the second data area from the number of the logical units mapped to the physical units in the first data area,

wherein the step of determining whether the erase count difference is larger than the erase count difference threshold comprises;

determining whether the erase count difference is larger than the erase count difference threshold and whether the logical unit amount difference is smaller than a logical unit amount difference threshold,

wherein the switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold and the logical unit amount difference is smaller than the logical unit amount difference threshold.

9. The memory management and writing method according to claim 1 further comprising:

configuring an erase count for the memory chip; and

determining whether the erase count is equal to a predetermined value when the write command corresponding to the first logical unit among the logical units and the new data corresponding to the write command are received,

wherein the step of determining whether the erase count difference is larger than the erase count difference threshold is executed when the erase count is equal to the predetermined value.

10. A rewritable non-volatile memory controller, for managing a plurality of physical units of a memory chip, the rewritable non-volatile memory controller comprising:

a microprocessor unit;

a rewritable non-volatile memory interface unit, coupled to the microprocessor unit, for coupling to the memory chip; and

a memory management unit, coupled to the microprocessor unit, wherein the memory management unit has a plurality of program codes, and the microprocessor unit executes the program codes to execute;

configuring a plurality of logical units;

grouping the physical units into a first physical unit group and a second physical unit group;

grouping a portion of the physical units in the first physical unit group into a first data area and a first spare area corresponding to the first data area;

grouping a portion of the physical units in the second physical unit group into a second data area and a second spare area corresponding to the second data area;

mapping the logical units to the physical units in the first data area and the second data area;

recording erase counts corresponding to a plurality of the physical units in the first physical unit group and the second physical unit group;

calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group according to the erase counts, and calculating an erase count difference between the first erase count and the second erase count; and

determining whether the erase count difference is larger than an erase count difference threshold when a write command corresponding to a first logical unit among the logical units and new data corresponding to the write command are received, wherein the first logical unit is mapped to a first physical unit among the physical units in the first data area,

wherein a switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold, and the switched writing procedure comprises;

getting a second physical unit from the physical units in the second spare area; and

writing the new data into the second physical unit.

11. The rewritable non-volatile memory controller according to claim 10, wherein the switched writing procedure further comprises:

associating the second physical unit to the second data area and re-mapping the first logical unit to the second physical unit.

12. The rewritable non-volatile memory controller according to claim 10, wherein the memory management unit executes a general writing procedure when the erase count difference is not larger than the erase count difference threshold, and the general writing procedure comprises:

getting a third physical unit from the physical units in the first spare area; and

writing the new data into the third physical unit.

13. The rewritable non-volatile memory controller according to claim 11, wherein the microprocessor unit further calculates a logical unit amount difference and determines whether the logical unit amount difference is equal to a logical unit amount difference threshold, wherein the logical unit amount difference is obtained by deducting the number of the logical units mapped to the physical units in the second data area from the number of the logical units mapped to the physical units in the first data area,

wherein the memory management unit further executes a wear levelling procedure when the logical unit amount difference is equal to the logical unit amount difference threshold, and the wear levelling procedure comprises:

getting a fourth physical unit from the physical units in the first spare area;

getting a fifth physical unit from the physical units in the second data area, wherein the fifth physical unit is mapped to a second logical unit among the logical units;

moving valid data in the third logical unit to the fourth physical unit; and

associating the fourth physical unit to the first data area, associating the fifth physical unit to the second spare area, and re-mapping the second logical unit to the fourth physical unit.

14. The rewritable non-volatile memory controller according to claim 10, wherein the microprocessor unit further calculates a logical unit amount difference, wherein the logical unit amount difference is obtained by deducting the number of the logical units mapped to the physical units in the second data area from the number of the logical units mapped to the physical units in the first data area,

wherein the procedure of determining whether the erase count difference is larger than the erase count difference threshold comprises:

determining whether the erase count difference is larger than the erase count difference threshold and whether the logical unit amount difference is smaller than a logical unit amount difference threshold,

wherein the switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold and the logical unit amount difference is smaller than the logical unit amount difference threshold.

15. A rewritable non-volatile memory storage system, comprising:

a connector;

a memory chip, having a plurality of physical units; and

a rewritable non-volatile memory controller, coupled to the memory chip and the connector, configured for executing;

configuring a plurality of logical units;

grouping the physical units into a first physical unit group and a second physical unit group;

grouping a portion of the physical units in the first physical unit group into a first data area and a first spare area corresponding to the first data area;

grouping a portion of the physical units in the second physical unit group into a second data area and a second spare area corresponding to the second data area;

mapping the logical units to the physical units in the first data area and the second data area;

recording erase counts corresponding to a plurality of the physical units in the first physical unit group and the second physical unit group;

calculating a first erase count of the first physical unit group and a second erase count of the second physical unit group according to the erase counts, and calculating an erase count difference between the first erase count and the second erase count; and

determining whether the erase count difference is larger than an erase count difference threshold when a write command corresponding to a first logical unit among the logical units and new data corresponding to the write command are received, wherein the first logical unit is mapped to a first physical unit among the physical units in the first data area,

wherein a switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold, and the switched writing procedure comprises;

getting a second physical unit from the physical units in the second spare area; and

writing the new data into the second physical unit.

16. The rewritable non-volatile memory storage system according to claim 15, wherein the switched writing procedure further comprises:

associating the second physical unit to the second data area and re-mapping the first logical unit to the second physical unit.

17. The rewritable non-volatile memory storage system according to claim 15, wherein the rewritable non-volatile memory controller executes a general writing procedure when the erase count difference is not larger than the erase count difference threshold, and the general writing procedure comprises:

getting a third physical unit from the physical units in the first spare area; and

writing the new data into the third physical unit.

18. The rewritable non-volatile memory storage system according to claim 17, wherein the general writing procedure further comprises:

moving valid data in the first physical unit to the third physical unit by using a copyback command set, wherein the copyback command set is used for reproducing and writing data in the memory chip.

19. The rewritable non-volatile memory storage system according to claim 17, wherein the general writing procedure further comprises:

associating the third physical unit to the first data area, and re-mapping the first logical unit to the third physical unit.

20. The rewritable non-volatile memory storage system according to claim 16, wherein the rewritable non-volatile memory controller further calculates a logical unit amount difference and determines whether the logical unit amount difference is equal to a logical unit amount difference threshold, wherein the logical unit amount difference is obtained by deducting the number of the logical units mapped to the physical units in the second data area from the number of the logical units mapped to the physical units in the first data area,

Wherein the rewritable non-volatile memory controller further executes a wear levelling procedure when the logical unit amount difference is equal to the logical unit amount difference threshold, and the wear levelling procedure comprises:

getting a fourth physical unit from the physical units in the first spare area;

getting a fifth physical unit from the physical units in the second data area, wherein the fifth physical unit is mapped to a second logical unit among the logical units;

moving valid data in the third logical unit to the fourth physical unit; and

associating the fourth physical unit to the first data area, associating the fifth physical unit to the second spare area, and re-mapping the second logical unit to the fourth physical unit.

21. The rewritable non-volatile memory storage system according to claim 15, wherein the physical units in the memory chip respectively belong to a first plane and a second plane,

wherein the rewritable non-volatile memory controller groups the physical units belonging to the first plane into the first physical unit group and the physical units belonging to the second plane into the second physical unit group,

wherein data corresponding to the first plane cannot be copied to the second plane by the copyback command set, and data corresponding to the second plane cannot be copied to the first plane by the copyback command set.

22. The rewritable non-volatile memory storage system according to claim 15, wherein the rewritable non-volatile memory controller further calculates a logical unit amount difference, wherein the logical unit amount difference is obtained by deducting a number of the logical units mapped to the physical units in the second data area from a number of the logical units mapped to the physical units in the first data area,

wherein the procedure of determining whether the erase count difference is larger than the erase count difference threshold comprises:

determining whether the erase count difference is larger than the erase count difference threshold and whether the logical unit amount difference is smaller than a logical unit amount difference threshold,

wherein the switched writing procedure is executed when the erase count difference is larger than the erase count difference threshold and the logical unit amount difference is smaller than the logical unit amount difference threshold.

23. The rewritable non-volatile memory storage system according to claim 15, wherein the rewritable non-volatile memory controller further configures an erase count for the memory chip,

wherein the rewritable non-volatile memory controller further determines whether the erase count is equal to a predetermined value when the write command corresponding to the first logical unit among the logical units and the new data corresponding to the write command are received,

wherein the procedure of determining whether the erase count difference is larger than the erase count difference threshold is executed when the erase count is equal to the predetermined value.

24. The rewritable non-volatile memory storage system according to claim 15, wherein the memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages of each of the physical blocks are individually written and simultaneously erased,

wherein the physical units are composed of the physical blocks.