High Endurance Non-Volatile Memory Devices

• US 20110197017A1
• Filed: 04/19/2011
• Published: 08/11/2011
• Est. Priority Date: 01/06/2000
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Shen, Ming-Shiang, Lee, Charles C., Chow, David Q., Ma, Abraham Chih-Kang, Yu, I-Kang
• Granted Patent: US 8,019,943 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Claims

1. A non-volatile memory device (NVMD) comprising:

a central processing unit (CPU);

a data cache subsystem coupled to the CPU, said data cache subsystem being initialized by a method comprises;

(a) receiving a power on or reset signal in the NVMD;

(b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM;

(c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number;

(d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and

repeating (a)-(d) for another block of the first type of NVM until there is no more blocks;

at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM;

a NVM controller, coupling to the CPU, configured for managing said at least one NVM module; and

an input/output (I/O) interface, coupling to the NVM controller, configured for receiving incoming data from the host to the data cache subsystem and configured for sending outgoing data from the data cache subsystem to the host.

2. The device of claim 1, wherein the first type and the second type are so configured that data programming to the second type is minimized.

3. The device of claim 1, wherein the first type of NVM and the second type of NVM comprises same size of data page.

4. The device of claim 1, wherein capacity of the first type of NVM is smaller than that of the second type of NVM and larger than that of the data cache subsystem.

5. The device of claim 1, wherein the first type of NVM comprises Single-Level Cell flash memory and the second type of NVM comprises Multi-Level Cell flash memory.

6. The device of claim 1, wherein the at least one NVM module comprises one of flash memory, phase-change memory, Magnetoresistive random access memory, Ferroelectric random access memory, and Nano random access memory.

7. The device of claim 1, wherein the data cache subsystem comprises at least one level of data cache.

8. The device of claim 7, wherein the data cache subsystem is one of a multiple-set associative cache system and a direct mapping cache system.

9. The device of claim 1, wherein said I/O interface comprises one of Advanced Technology Attachment (ATA), Serial ATA (SATA), Small Computer System Interface (SCSI), Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) Express, ExpressCard, fiber channel Interface, optical connection interface circuit, and Secure Digital.

11. The device of claim 1, wherein the first type of NVM is single-level cell flash memory while the second type of NVM is multi-level cell flash memory.

12. The device of claim 1, wherein said data cache subsystem comprises phase-change memory and said at least one non-volatile memory comprises single-level cell flash memory.

13. The device of claim 1, wherein said data cache subsystem comprises phase-change memory and wherein said at least one non-volatile memory comprises multi-level cell flash memory.

14. The device of claim 1, wherein said data cache subsystem comprises dynamic random memory and said at least one non-volatile memory comprises single-level cell flash memory.

15. The device of claim 1, wherein said data cache subsystem comprises dynamic random memory and said at least one non-volatile memory comprises multi-level cell flash memory.

10. (canceled)

16. A multi-processor non-volatile memory device (NVMD) comprising:

a plurality of internal non-volatile memory devices;

a first central processing unit (CPU) configured for managing and controlling the plurality of internal non-volatile memory devices coupled therewith, wherein each of the plurality of internal non-volatile memory devices includes;

a second CPU;

a data cache subsystem coupled to the second CPU, said data cache subsystem being initialized by a method comprises;

(a) receiving a power on or reset signal in the NVMD;

(b) retrieving a tag, an index, a set number and a number-of-hits flag from a spare area of a first page of a block in the first type of NVM;

(c) loading stored data from data area of all of the pages of the block of the first type of NVM into a particular cache line in the data cache subsystem when the particular cache line is empty, wherein the particular cache line is determined by the retrieved index and the retrieved set number;

(d) otherwise loading the stored data from data area of all of the pages of the block of the first type of NVM into the particular cache line only if the retrieved number-of-hits flag shows a number greater than number-of-hits already stored in the cache line; and

repeating (a)-(d) for another block of the first type of NVM until there is no more blocks; and

at least one non-volatile memory (NVM) module configured as a data storage of a host as the NVMD is operatively adapted to the host, said at least one non-volatile memory module having first and second types of NVM arranged in a hierarchical scheme with the first type of NVM configured as a buffer between the data cache subsystem and the second type of NVM.

17. The device of claim 16, wherein said data cache subsystem comprises dynamic random memory.

18. The device of claim 16, wherein said data cache subsystem comprises phase-change memory.

19. The device of claim 16, wherein the first type of NVM is single-level cell flash memory while the second type of NVM is multi-level cell flash memory.

20. (canceled)