NON-VOLATILE MEMORY DEVICE AND DATA PROCESSING METHOD THEREOF

• US 20110197107A1
• Filed: 05/24/2010
• Published: 08/11/2011
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: OU, Hsu-Ping
• Granted Patent: US 8,392,794 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc

Abstract

A data processing method for a non-volatile memory device is provided. The non-volatile memory device includes a controller and a NAND flash memory. First, a target command and a corresponding target address are serially transmitted from the controller to the NAND flash memory. Then, the NAND flash memory calculates a first value according to the target address. Moreover, a cyclic redundancy check code corresponding to the target address is transmitted from the controller transmits to the NAND flash memory. Next, the NAND flash memory determines whether a transmission error has occurred by performing a cyclic redundancy check according to the first value and the cyclic redundancy check code. When the transmission error has occurred, a status register is set to inform the controller to re-transmit the target command and the corresponding target address.

Claims

1. A data processing method for a non-volatile memory device, wherein the non-volatile memory device comprises a controller and a NAND flash memory and the data processing method comprises the steps of:

serially transmitting a target command and a corresponding target address from the controller to the NAND flash memory;

calculating a first value according to the target address by the NAND flash memory;

transmitting a cyclic redundancy check code corresponding to the target address from the controller to the NAND flash memory;

performing a cyclic redundancy check on the NAND flash memory according to the first value and the cyclic redundancy check code to determine whether a transmission error has occurred; and

if the transmission error has occurred, setting a status register to inform the controller to re-transmit the target command and the corresponding target address.

2. The data processing method as claimed in claim 1, wherein the NAND flash memory calculates the first value in response to a first cyclic redundancy check command received from the controller.

3. The data processing method as claimed in claim 1, further comprising the steps of:

determining whether the target command is a write command;

if the target command is the write command, serially transmitting a write data corresponding to the write command from the controller to the NAND flash memory;

calculating a second value according to the write data by the NAND flash memory;

transmitting another cyclic redundancy check code corresponding to the write data from the controller to the NAND flash memory;

performing the cyclic redundancy check on the NAND flash memory according to the second value and the another cyclic redundancy check code to determine whether the transmission error has occurred; and

if the transmission has occurred, setting the status register to inform the controller to re-transmit the write command and the corresponding target address.

4. The data processing method as claimed in claim 3, wherein the NAND flash memory calculates the second value in response to a second cyclic redundancy check command received from the controller.

5. The data processing method as claimed in claim 3, further comprising the steps of:

if there is no transmission error of the target address and the write data, performing a programming operation on the NAND flash memory according to the target address corresponding to the write command and the write data.

6. The data processing method as claimed in claim 1, further comprising the steps of:

determining whether the target command is an erase command;

if the target command is the erase command, and there is no transmission error of the target address, performing an erase operation on the NAND flash memory according to the target address.

7. A data processing method for a non-volatile memory device, wherein the non-volatile memory device comprises a controller and a NAND flash memory and the data processing method comprises the steps of:

serially transmitting a read command and a corresponding read address from the controller to the NAND flash memory;

performing a read operation on the NAND flash memory according to the read address and serially transmitting predetermined data to the controller;

calculating a first value according to the predetermined data by the controller,

transmitting a cyclic redundancy check code corresponding to the predetermined data from the NAND flash memory to the controller;

performing a cyclic redundancy check on the controller according to the first value and the cyclic redundancy check code to determine whether a transmission error has occurred; and

if the transmission error has occurred, informing the controller to re-transmit the read command and the corresponding read address.

8. The data processing method as claimed in claim 7, wherein the NAND flash memory transmits the cyclic redundancy check code to the controller in response to a cyclic redundancy check command received from the controller.

9. A non-volatile memory device, comprising:

a controller for providing a target command and a corresponding target address;

a bus for serially transmitting the target command and the corresponding target address; and

a NAND flash memory coupled to the controller via the bus, comprising;

a NAND flash array;

an input/output circuit for receiving the target command and the corresponding target address; and

an engine coupled to the input/output circuit for calculating a first value according to the target address and performing a cyclic redundancy check according to the first value and a cyclic redundancy check code corresponding to the target address received from the controller to determine whether a transmission error has occurred,

wherein if the transmission error has occurred, the engine sets a status register to inform the controller to re-transmit the target command and the corresponding target address.

10. The non-volatile memory device as claimed in claim 9, wherein the engine calculates the first value in response to a first cyclic redundancy check command received from the controller.

11. The non-volatile memory device as claimed in claim 9, wherein the input/output circuit further determines whether the target command is a write command and receives a write data corresponding to the write command from the controller when the target command is the write command, and the engine calculates a second value according to the write data and performs the cyclic redundancy check according to the second value and another cyclic redundancy check code corresponding to the write data received from the controller to determine whether the transmission error has occurred, and wherein if the transmission error has occurred, the engine sets the status register to inform the controller to re-transmit the target command and the corresponding target address.

12. The non-volatile memory device as claimed in claim 11, wherein the engine calculates the second value in response to a second cyclic redundancy check command received from the controller.

13. The non-volatile memory device as claimed in claim 11, wherein if there is no transmission error of the target address and the write data, the NAND flash array performs a programming operation according to the target address and the write data corresponding to the write command.

14. The non-volatile memory device as claimed in claim 9, wherein the input/output circuit further determines whether the target command is an erase command, and if the target command is the erase command and there is no transmission error of the target address, the NAND flash array performs an erase operation according to the target address.

15. A non-volatile memory device, comprising:

a controller for providing a read command and a corresponding read address;

a bus for serially transmitting the read command and the corresponding read address; and

a NAND flash memory coupled to the controller via the bus, comprising;

a NAND flash array for performing a read operation according to the read address;

an input/output circuit for serially transmitting predetermined data read from the NAND flash array to the controller via the bus; and

an engine coupled to the input/output circuit for transmitting a cyclic redundancy check code corresponding to the predetermined data to the controller,

wherein the controller calculates a first value according to the predetermined data and performs a cyclic redundancy check according to the first value and the cyclic redundancy check code to determine whether a transmission error has occurred, and

wherein if the transmission error has occurred, the controller re-transmits the read command and the corresponding read address.

16. The non-volatile memory device as claimed in claim 15, wherein the engine transmits the cyclic redundancy check code to the controller in response to a cyclic redundancy check command received from the controller.